Alternatives and similar repositories for 16-bit-risc-processor

Users that are interested in 16-bit-risc-processor are comparing it to the libraries listed below

• zeeshanrafique23 / RV32I-Logisim
  RV32I single cycle simulation on open-source software Logisim.
  ☆21Updated 3 years ago
• rolandbernard / kleine-riscv
  A small and simple rv32i core written in Verilog
  ☆17Updated 3 years ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆35Updated 2 years ago
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆65Updated 6 months ago
• olofk / qerv
  ☆19Updated 7 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆62Updated 2 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆81Updated 5 years ago
• aniketnk / circular-queue-verilog
  Implementation of a circular queue in hardware using verilog.
  ☆17Updated 6 years ago
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆56Updated 2 years ago
• mrisc32 / mc1
  A computer (FPGA SoC) based on the MRISC32-A1 CPU
  ☆54Updated 2 years ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆78Updated 3 years ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆62Updated last year
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆47Updated this week
• AntonMause / rv16poc
  16 bit RISC-V proof of concept
  ☆24Updated 2 months ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆37Updated this week
• thinkoco / de10-nano-riscv
  A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano
  ☆40Updated 5 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 9 months ago
• ultraembedded / altor32
  AltOr32 - Alternative Lightweight OpenRisc CPU
  ☆13Updated 10 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆38Updated last year
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆54Updated 7 years ago
• TobiasFaller / gcc-riscv-elf-rv32e-rv32i-rv64i
  Build script to compile an up-to-date RISC-V GCC toolchain on Debian / Ubuntu with rv32e, rv32i and rv64i architectures and ilp32e, ilp3…
  ☆11Updated 4 months ago
• Wren6991 / DOOMSoC
  A SoC for DOOM
  ☆19Updated 4 years ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆58Updated 5 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆70Updated 3 years ago
• jbush001 / MiteCPU
  Minimal microprocessor
  ☆21Updated 8 years ago
• mrisc32 / mrisc32-a1
  A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
  ☆24Updated 2 years ago
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆47Updated 3 years ago
• ecilasun / NekoIchi
  A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board
  ☆31Updated 4 years ago
• AEW2015 / fpga-colab
  FPGA examples on Google Colab
  ☆27Updated 4 months ago
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆27Updated 2 months ago