Alternatives and similar repositories for 16-bit-risc-processor

Users that are interested in 16-bit-risc-processor are comparing it to the libraries listed below

• mrisc32 / mrisc32-a1
  A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
  ☆24Updated 2 years ago
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆65Updated 7 months ago
• freecores / sparc64soc
  OpenSPARC-based SoC
  ☆74Updated 11 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆71Updated 3 years ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆75Updated last week
• zeeshanrafique23 / RV32I-Logisim
  RV32I single cycle simulation on open-source software Logisim.
  ☆21Updated 3 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆57Updated 2 years ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆41Updated 3 years ago
• dan-rodrigues / caravel_vdp_lite
  ☆20Updated 5 years ago
• jbush001 / MiteCPU
  Minimal microprocessor
  ☆21Updated 8 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆63Updated 2 years ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆34Updated 2 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆82Updated 5 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 9 months ago
• ultraembedded / altor32
  AltOr32 - Alternative Lightweight OpenRisc CPU
  ☆13Updated 10 years ago
• thinkoco / de10-nano-riscv
  A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano
  ☆40Updated 5 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆64Updated 4 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆49Updated 3 weeks ago
• mrisc32 / mc1
  A computer (FPGA SoC) based on the MRISC32-A1 CPU
  ☆54Updated 2 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆47Updated 3 weeks ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.
  ☆38Updated last week
• AntonMause / rv16poc
  16 bit RISC-V proof of concept
  ☆24Updated this week
• sylefeb / Silixel
  Exploring gate level simulation
  ☆59Updated 8 months ago
• danielkasza / 9444
  9444 RISC-V 64IMA CPU and related tools and peripherals.
  ☆27Updated 4 years ago
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆62Updated 4 years ago
• bwitherspoon / rv32cpu
  A RISC-V processor
  ☆15Updated 7 years ago
• PavlenkoG / ECP5_PCIE_Analyzer
  ☆17Updated 2 years ago
• aniketnk / circular-queue-verilog
  Implementation of a circular queue in hardware using verilog.
  ☆17Updated 6 years ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆64Updated last year