CNN-to-FPGA-framework for small CNN, written in VHDL and Python
☆23Jun 8, 2021Updated 4 years ago
Alternatives and similar repositories for pocket-cnn
Users that are interested in pocket-cnn are comparing it to the libraries listed below
Sorting:
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 4 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- serial com api☆38Dec 17, 2020Updated 5 years ago
- VHDL package for reading formatted data from comma-separated-values (CSV) files☆23Sep 10, 2013Updated 12 years ago
- Transfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA☆23May 20, 2019Updated 6 years ago
- AUTOMATIC VHDL GENERATION FOR CNN MODELS☆32Nov 16, 2022Updated 3 years ago
- Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"☆31Dec 10, 2021Updated 4 years ago
- pyVhdl2sch is a python based VHDL to (pdf) schematic converter☆33Oct 20, 2019Updated 6 years ago
- Triple Modular Redundancy☆30Sep 4, 2019Updated 6 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- ☆13Mar 2, 2023Updated 3 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- 适用于FPGA——利用串口通信接收幅度频率信息数据帧，控制DA输出相应正弦信号☆10Jul 10, 2019Updated 6 years ago
- Open Source ZYNQ Board☆31Aug 19, 2015Updated 10 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆45Jun 24, 2022Updated 3 years ago
- migen + misoc + redpitaya = digital servo☆41Jan 11, 2019Updated 7 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆16Sep 21, 2025Updated 5 months ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Oct 31, 2021Updated 4 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- Go Board FPGA Project for Ambient Light Sensor in VHDL and Verilog☆10Apr 20, 2019Updated 6 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- Python scripts for KiCad☆11Mar 21, 2016Updated 9 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- CGAL based FEMs for EIT from segmentation files☆11Nov 3, 2020Updated 5 years ago
- ☆11Sep 18, 2023Updated 2 years ago
- ☆11May 8, 2022Updated 3 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆15May 16, 2021Updated 4 years ago
- Open source digital FPGA based theremin project☆11Jul 13, 2021Updated 4 years ago
- Kernel Module that implements Paxos protocol☆12Oct 23, 2020Updated 5 years ago