marph91 / pocket-cnn
CNN-to-FPGA-framework for small CNN, written in VHDL and Python
☆19Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for pocket-cnn
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 6 years ago
- Generate testbench for your verilog module.☆35Updated 6 years ago
- IP operations in verilog (simulation and implementation on ice40)☆52Updated 5 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆13Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆97Updated 4 years ago
- General Purpose AXI Direct Memory Access☆44Updated 5 months ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆35Updated 11 months ago
- Adding PR to the PYNQ Overlay☆17Updated 7 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- Open FPGA Modules☆22Updated last month
- This repo contain the PY-UVM Framework for different RISC-V Cores☆31Updated last year
- Xilinx AXI VIP example of use☆31Updated 3 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆25Updated last week
- A simple DDR3 memory controller☆51Updated last year
- Extensible FPGA control platform☆53Updated last year
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- SRAM☆20Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- Learn about image processing with an FPGA. Video lectures explain algorithm and implementation of lane detection for automotive driving. …☆31Updated 5 months ago
- PYNQ Composabe Overlays☆67Updated 4 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆37Updated 3 years ago
- Matrix Multiply and Accumulate unit written in System Verilog☆10Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆30Updated last year
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated 10 months ago
- ☆32Updated last year
- Microshift Compression: An Efficient Image Compression Algorithm for Hardware☆32Updated 3 years ago
- Video Stream Scaler☆40Updated 10 years ago
- The Verilog source code for DRUM approximate multiplier.☆27Updated last year