Alternatives and similar repositories for eie1_fpga_lab

Users that are interested in eie1_fpga_lab are comparing it to the libraries listed below

• LangProc / langproc_2015_cw
  ☆6Updated 8 years ago
• m8pple / arch2-2016-cw
  ☆10Updated 8 years ago
• martinferianc / C90Compiler-EIE2
  C90 to MIPS I Compiler done as a coursework for EE2-15
  ☆16Updated 5 years ago
• martinferianc / relax
  💤 Relaxation labelling to refine edge detection 💤
  ☆11Updated 5 years ago
• good-data-movement / manifesto
  The Good Data Movement manifesto.
  ☆14Updated 5 years ago
• jofrfu / tinyTPU
  Implementation of a Tensor Processing Unit for embedded systems and the IoT.
  ☆477Updated 6 years ago
• Xilinx / RFNoC-HLS-NeuralNet
  ☆107Updated 5 years ago
• mtmd / FPGA_Based_CNN
  FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
  ☆181Updated 8 years ago
• Xilinx / PYNQ-ComputerVision
  Computer Vision Overlays on Pynq
  ☆179Updated 5 years ago
• myhdl / myhdl
  The MyHDL development repository
  ☆1,084Updated 2 months ago
• Xilinx / PYNQ-DL
  Xilinx Deep Learning IP
  ☆92Updated 4 years ago
• KastnerRG / pp4fpgas
  Parallel Programming for FPGAs -- An open-source high-level synthesis book
  ☆838Updated 5 months ago
• beetleboxorg / sign_language_mnist
  Tutorial for Vitis AI using the Sign Language MNIST
  ☆17Updated 2 years ago
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆721Updated last year
• vmware-archive / cascade
  A Just-In-Time Compiler for Verilog from VMware Research
  ☆445Updated 3 years ago
• Xilinx / finn
  Dataflow compiler for QNN inference on FPGAs
  ☆835Updated this week
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆87Updated 4 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆106Updated last month
• NetFPGA / netfpga
  NetFPGA 1G infrastructure and gateware
  ☆377Updated 6 years ago
• changwoolee / lenet5_hls
  FPGA Accelerator for CNN using Vivado HLS
  ☆317Updated 3 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆198Updated 3 weeks ago
• Xilinx / SDSoC-Tutorials
  SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials
  ☆154Updated 5 years ago
• Xilinx / finn-examples
  Dataflow QNN inference accelerator examples on FPGAs
  ☆218Updated 3 months ago
• ZFTurbo / Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA
  Verilog Generator of Neural Net Digit Detector for FPGA
  ☆312Updated 2 years ago
• alan4186 / Hardware-CNN
  A convolutional neural network implemented in hardware (verilog)
  ☆159Updated 7 years ago
• johnzja / PolarDecoder
  PolarDecoders implemented in Verilog. SC, SCL, CA-SCL and CA-PC-SCL are supported.
  ☆7Updated 3 years ago
• fastmachinelearning / hls4ml-tutorial
  Tutorial notebooks for hls4ml
  ☆346Updated last month
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆348Updated 5 months ago
• fpgasystems / spooNN
  FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)
  ☆273Updated 5 years ago
• will-zegers / fpga_cnn
  Convolutional Neural Net written for implementation on an FPGA
  ☆21Updated 8 years ago