m8pple / eie1_fpga_lab
Spring term two-week FPGA lab for EIE students
☆7Updated 8 years ago
Alternatives and similar repositories for eie1_fpga_lab:
Users that are interested in eie1_fpga_lab are comparing it to the libraries listed below
- ☆6Updated 8 years ago
- ☆10Updated 8 years ago
- The Good Data Movement manifesto.☆14Updated 5 years ago
- ☆101Updated last month
- Dataflow compiler for QNN inference on FPGAs☆806Updated last week
- 💤 Relaxation labelling to refine edge detection 💤☆11Updated 5 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆103Updated 5 months ago
- Verilog AXI stream components for FPGA implementation☆796Updated last month
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆26Updated last week
- C90 to MIPS I Compiler done as a coursework for EE2-15☆16Updated 5 years ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆444Updated last week
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆700Updated 10 months ago
- A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…☆270Updated last month
- VUnit is a unit testing framework for VHDL/SystemVerilog☆768Updated 3 weeks ago
- An abstraction library for interfacing EDA tools☆684Updated 2 weeks ago
- Verilog Generator of Neural Net Digit Detector for FPGA☆312Updated 2 years ago
- EPFL logic synthesis benchmarks☆185Updated 7 months ago
- A collection of Master XDC files for Digilent FPGA and Zynq boards.☆572Updated 5 months ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,082Updated this week
- Getting Started with Xilinx ML Suite☆337Updated 4 years ago
- Hardcaml is an OCaml library for designing hardware.☆741Updated 5 months ago
- Research paper based on or related to ABC.☆36Updated 2 weeks ago
- A logic synthesis tool☆73Updated 2 weeks ago
- Binarized Convolutional Neural Networks on Software-Programmable FPGAs☆303Updated 4 years ago
- Parallel Programming for FPGAs -- An open-source high-level synthesis book☆826Updated 3 months ago
- Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…☆354Updated 3 weeks ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆291Updated last month
- ☆670Updated 5 months ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆458Updated 6 years ago
- SystemVerilog compiler and language services☆729Updated this week