Alternatives and similar repositories for fpga_project_skeleton_fa22

Users that are interested in fpga_project_skeleton_fa22 are comparing it to the libraries listed below

• OSCPU / yosys-sta
  ☆72Updated 2 months ago
• 2horse9sun / ucb_sp20_cs152_lab
  UC Berkeley CS152 Computer Architecture and Engineering Labs
  ☆25Updated 5 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆68Updated 2 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆171Updated 8 months ago
• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆41Updated 2 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆24Updated last month
• XS-MLVP / env-xs-ov-00-bpu
  香山微架构开放验证第一期：昆明湖BPU模块UT测试模块及环境
  ☆29Updated 8 months ago
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆25Updated 2 years ago
• NamanMakkar / ECE5545-ML-Hardware-Systems
  This repo contains the Assignments from Cornell Tech's ECE 5545 - Machine Learning Hardware and Systems offered in Spring 2023
  ☆32Updated 2 years ago
• OpenXiangShan / GEM5
  ☆86Updated this week
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆146Updated 2 years ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆27Updated 3 years ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 10 months ago
• EECS150 / fpga_labs_fa22
  ☆20Updated 2 years ago
• datenlord / training
  ☆10Updated last year
• OSCPU / ysyxSoC
  ☆86Updated last month
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆50Updated 2 weeks ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆102Updated 4 months ago
• vortexgpgpu / vortex_tutorials
  ☆174Updated 2 weeks ago
• luzhixing12345 / archlab
  NUDT 高级体系结构实验
  ☆35Updated 9 months ago
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆24Updated 2 years ago
• USTC-System-Courses / CECS-Lab
  ☆38Updated last year
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆48Updated last year
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆203Updated 3 weeks ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆64Updated last year
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆57Updated 3 months ago
• OSCPU / chisel-playground
  ☆68Updated 4 months ago
• EECS150 / fpga_labs_sp22
  ☆30Updated 3 years ago