Alternatives and similar repositories for riscv-meta

Users that are interested in riscv-meta are comparing it to the libraries listed below

• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆100Updated 2 years ago
• lcq2 / risc-666
  RISC-V user-mode emulator that runs DooM
  ☆53Updated 6 years ago
• shacron / sled
  Sled System Emulator
  ☆28Updated 2 months ago
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆42Updated 7 years ago
• alastairreid / mra_tools
  Tools to process ARM's Machine Readable Architecture Specification
  ☆131Updated 5 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆49Updated 8 years ago
• michaeljclark / busybear-linux
  busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu.
  ☆98Updated last year
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 2 months ago
• openrisc / llvm-or1k
  LLVM backend for OpenRISC 1000
  ☆29Updated 7 years ago
• atgreen / moxie-cores
  Moxie-compatible core repository
  ☆46Updated last year
• CTSRD-CHERI / qemu
  QEMU with support for CHERI
  ☆58Updated 2 weeks ago
• defparam / higan-verilog
  This is a higan/Verilator co-simulation example/framework
  ☆50Updated 7 years ago
• noteed / riscv-hello-c
  Bare metal RISC-V hello world in C
  ☆19Updated 6 years ago
• riscv-non-isa / riscv-device-tree-doc
  RISC-V Specific Device Tree Documentation
  ☆42Updated last year
• ARM-software / asl-interpreter
  Example implementation of Arm's Architecture Specification Language (ASL)
  ☆118Updated 5 years ago
• TUD-OS / NUL
  NOVA userland
  ☆48Updated 11 years ago
• nspin / hs-arm
  (Dis)assembler and analyzer generated from the machine-readable ARMv8.3-A specification
  ☆27Updated 7 years ago
• dougallj / asil
  ☆32Updated last year
• azonenberg / antikernel
  The Antikernel operating system project
  ☆121Updated 5 years ago
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 2 years ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆53Updated 4 years ago
• racerxdl / riscv-online-asm
  RISC-V Online Assembler using Emscripten, Gnu Binutils
  ☆55Updated last year
• bit-hack / riscv-vm
  A Small RISC-V Virtual Machine
  ☆80Updated 3 years ago
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• nbdd0121 / r2vm
  Rust RISC-V Virtual Machine
  ☆105Updated 8 months ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆85Updated 5 years ago
• seL4 / util_libs
  ☆59Updated last month
• mausimus / rvcc
  Standalone C compiler for RISC-V and ARM
  ☆87Updated last year
• rems-project / sail-arm
  Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
  ☆80Updated 2 weeks ago
• lowRISC / rocket
  ☆32Updated 7 years ago