Alternatives and similar repositories for logi-pong-chu-examples

Users that are interested in logi-pong-chu-examples are comparing it to the libraries listed below

• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆38Updated 4 years ago
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆36Updated 4 years ago
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆24Updated 4 years ago
• fpga-logi / logi-hard
  All Logi specific HDL code (platform specific interface, extension boards, specific hdl, etc)
  ☆31Updated 9 years ago
• jakubcabal / rmii-firewall-fpga
  RMII Firewall FPGA
  ☆24Updated 5 years ago
• Cognoscan / BoostDSP
  VHDL Library for implementing common DSP functionality.
  ☆30Updated 6 years ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆23Updated last year
• open-design / riscv-soc-cores
  ☆38Updated 4 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• suoto / fpga_cores
  ☆32Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 6 months ago
• jakubcabal / uart-for-fpga
  Simple UART controller for FPGA written in VHDL
  ☆102Updated 4 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 4 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆34Updated 6 months ago
• noasic / noasic
  An open-source VHDL library for FPGA design.
  ☆31Updated 3 years ago
• PyLCARS / PythonUberHDL
  Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL
  ☆36Updated 6 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆87Updated 2 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆64Updated 2 years ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆27Updated 2 weeks ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆80Updated 4 years ago
• controlpaths / blog
  Projects published on controlpaths.com and hackster.io
  ☆41Updated 3 years ago
• oetr / FPGA-I2C-Minion
  A simple I2C minion in VHDL
  ☆61Updated 5 years ago
• ldoolitt / vhd2vl
  ☆136Updated 8 months ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆30Updated 5 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆29Updated 6 months ago
• MJoergen / HyperRAM
  Portable HyperRAM controller
  ☆58Updated 8 months ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• sam210723 / fpga
  Collection of projects for various FPGA development boards
  ☆45Updated last year