jonsonxp / sea_azprLinks
An AZPR SoC implementation on SEA FPGA Board.
☆9Updated 4 years ago
Alternatives and similar repositories for sea_azpr
Users that are interested in sea_azpr are comparing it to the libraries listed below
Sorting:
- SPI-Flash XIP Interface (Verilog)☆38Updated 3 years ago
- OpenFPGA ICE40UP5K☆33Updated 4 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆90Updated 5 years ago
- FPGA implementation of the 8051 Microcontroller (Verilog)☆48Updated 10 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆28Updated last year
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen☆19Updated 10 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆27Updated 6 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- Small (Q)SPI flash memory programmer in Verilog☆63Updated 2 years ago
- USB serial device (CDC-ACM)☆38Updated 4 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- ☆40Updated 4 years ago
- Reindeer Soft CPU for Step CYC10 FPGA board☆27Updated 4 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆55Updated last year
- Verilog SPI master and slave☆54Updated 9 years ago
- Connecting FPGA and Arduino using SPI.☆25Updated 3 years ago
- Collection of projects for various FPGA development boards☆44Updated last year
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆37Updated 3 years ago
- Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board☆16Updated 3 years ago
- MIPI CSI-2 Camera Sensor Receiver V2 Verilog HDL implementation For any generic FPGA. Tested with IMX219 IMX477 on Lattice Crosslink NX w…☆56Updated 3 months ago
- USB 1.1 Host and Function IP core☆23Updated 10 years ago
- Digital FM Radio Receiver for FPGA☆60Updated 9 years ago
- FT2232HL JTAG & UART Downloader☆15Updated 3 years ago
- ☆14Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- MMC (and derivative standards) host controller☆24Updated 4 years ago