This linter plugin for SublimeLinter provides an interface to iverilog (verilog compiler).
☆13Apr 16, 2024Updated 2 years ago
Alternatives and similar repositories for SublimeLinter-contrib-iverilog
Users that are interested in SublimeLinter-contrib-iverilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The VD100 development board is based on the Xilinx Versal AI Edge series chip xcve2302 and is designed with a core board and a bottom boa…☆18Jul 9, 2024Updated last year
- 👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)☆16Dec 8, 2025Updated 4 months ago
- 🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes…☆45Mar 27, 2026Updated 3 weeks ago
- GUI for SymbiYosys☆17Oct 13, 2025Updated 6 months ago
- lightweight open HLS for FPGA rapid prototyping☆20Mar 22, 2018Updated 8 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 7 years ago
- Next-Generation FPGA Place-and-Route☆10Aug 1, 2018Updated 7 years ago
- Xilinx IP repository☆13May 5, 2018Updated 7 years ago
- Hardware Trojan on a Basis 3 FPGA for Hardware and Embedded Systems Security☆11May 1, 2017Updated 8 years ago
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆11Feb 28, 2015Updated 11 years ago
- Used for hardware trojan detection（Based on Trust_Hub）☆10Jul 30, 2019Updated 6 years ago
- 视频旋转（2019FPGA大赛）☆41May 5, 2020Updated 5 years ago
- Translation of the `Managing projects with GNU make' book to Russian.☆12May 26, 2013Updated 12 years ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A vhdl package for reading and writing bitmap files.☆12Jan 9, 2018Updated 8 years ago
- Adds Switch's UI sounds to your keyboard presses.☆11Jun 23, 2022Updated 3 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- A bearlibterminal wrapper☆17Nov 1, 2020Updated 5 years ago
- A collection of SPI related cores☆21Nov 12, 2024Updated last year
- Sublime Text 非官方中文语言包☆10Dec 15, 2025Updated 4 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆18Feb 22, 2026Updated last month
- CRC Theory and Implement. explain initial value of CRC☆16Feb 26, 2021Updated 5 years ago
- A Sublime Text plugin that displays inline images for single-line comments formatted like `// `.☆12May 16, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Line Hyper-eXpander, a sed/awk-like text processing tool with a human face :)☆15Feb 10, 2026Updated 2 months ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Dec 1, 2018Updated 7 years ago
- SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)☆11Jun 19, 2024Updated last year
- Synchronous FIFOs designed in Verilog/System Verilog.☆25Dec 21, 2025Updated 3 months ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆23Nov 10, 2024Updated last year
- This is a cool UWP DeveloperTool that includes Brushes, Styles, Controls, ColorPicker, open source projects made with Win2d☆15Jun 23, 2021Updated 4 years ago
- SystemVerilog plugin for Sublime Text☆49Mar 28, 2026Updated 3 weeks ago
- SystemVerilog extension for Visual Studio Code☆14Dec 18, 2018Updated 7 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆33Apr 8, 2026Updated last week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Jan 9, 2019Updated 7 years ago
- ☆80Feb 5, 2022Updated 4 years ago
- 常用Verilog模块☆20Mar 3, 2020Updated 6 years ago
- Hardware Security Labs☆31May 3, 2017Updated 8 years ago
- PCIe library for the Xilinx 7 series FPGAs in the Bluespec language☆82Mar 22, 2022Updated 4 years ago
- 云编译RAX3000M-eMMC闭源固件并整理保存其他大佬的798x\762x\固件☆24Jun 12, 2025Updated 10 months ago
- Generate UVM testbench framework template files with Python 3☆26Dec 23, 2019Updated 6 years ago