This linter plugin for SublimeLinter provides an interface to iverilog (verilog compiler).
☆13Apr 16, 2024Updated 2 years ago
Alternatives and similar repositories for SublimeLinter-contrib-iverilog
Users that are interested in SublimeLinter-contrib-iverilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- sublimetext verilog syntax highlighting☆12Sep 7, 2016Updated 10 years ago
- The VD100 development board is based on the Xilinx Versal AI Edge series chip xcve2302 and is designed with a core board and a bottom boa…☆20Jul 9, 2024Updated 2 years ago
- 👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)☆17May 14, 2026Updated 4 months ago
- 🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes…☆46Mar 27, 2026Updated 5 months ago
- Verilog Package for Sublime Text 2/3☆23Jan 27, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- lightweight open HLS for FPGA rapid prototyping☆20Mar 22, 2018Updated 8 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 7 years ago
- Next-Generation FPGA Place-and-Route☆10Aug 1, 2018Updated 8 years ago
- Hardware Trojan on a Basis 3 FPGA for Hardware and Embedded Systems Security☆11May 1, 2017Updated 9 years ago
- Testing tools (binary/text) for RS232, QTcpSocket, QLocalSocket☆13Dec 22, 2015Updated 10 years ago
- A cross platform, formally verified, open source, hyperRAM controller with simulator☆17Feb 22, 2019Updated 7 years ago
- Used for hardware trojan detection(Based on Trust_Hub)☆10Jul 30, 2019Updated 7 years ago
- 视频旋转(2019FPGA大赛)☆42May 5, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- GUI for SymbiYosys☆18Aug 4, 2026Updated last month
- A vhdl package for reading and writing bitmap files.☆12Jan 9, 2018Updated 8 years ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Binary Content Addressable Memory (II-2D-BCAM)☆17Nov 10, 2024Updated last year
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 8 years ago
- Building FPGAs with Quartus+CMake☆18Aug 14, 2017Updated 9 years ago
- A Sublime Text plugin that displays inline images for single-line comments formatted like `// `.☆12May 16, 2024Updated 2 years ago
- Sublimerge is a Sublime Text 2 plugin which allows to diff and merge files DIRECTLY in the editor using graphical interface for that purp…☆16Dec 4, 2012Updated 13 years ago
- A bearlibterminal wrapper☆18Nov 1, 2020Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Sublime Text 非官方中文语言包☆11Dec 15, 2025Updated 9 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆19Sep 11, 2026Updated last week
- Line Hyper-eXpander, a sed/awk-like text processing tool with a human face :)☆15Feb 10, 2026Updated 7 months ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆23Nov 10, 2024Updated last year
- This is a cool UWP DeveloperTool that includes Brushes, Styles, Controls, ColorPicker, open source projects made with Win2d☆15Jun 23, 2021Updated 5 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆26Dec 21, 2025Updated 8 months ago
- ☆82Feb 5, 2022Updated 4 years ago
- Contains source code for sin/cos table verification using UVM☆23Mar 9, 2021Updated 5 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆35Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A collection of SPI related cores☆23Nov 12, 2024Updated last year
- 常用Verilog模块☆21Mar 3, 2020Updated 6 years ago
- Hardware Security Labs☆30May 3, 2017Updated 9 years ago
- Generate UVM testbench framework template files with Python 3☆26Dec 23, 2019Updated 6 years ago
- ☆21Apr 1, 2026Updated 5 months ago
- Xilinx 7-series FTDI-FPGA interface through JTAG with 125 us roundtrip latency☆22May 30, 2019Updated 7 years ago
- FPGA based 30ps RMS TDCs☆98Mar 18, 2018Updated 8 years ago