jankralx / comparator_dpdLinks
Adaptation of a predistorter (DPD) to linarize a power amplifier (PA) with a comparator in the feedback, based on the direct learning architecture (DLA).
☆13Updated 2 years ago
Alternatives and similar repositories for comparator_dpd
Users that are interested in comparator_dpd are comparing it to the libraries listed below
Sorting:
- Toy OFDM Communication System with FPGA☆12Updated 3 years ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆77Updated 2 years ago
- LMS sound filtering by Verilog☆44Updated 5 years ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆52Updated 8 years ago
- OpenDPD is an end-to-end learning framework built in PyTorch for power amplifier (PA) modeling and digital pre-distortion (DPD). You are …☆104Updated this week
- 最小和算法实现☆10Updated 5 years ago
- HSPICE and MATLAB simulation files of a tracking SAR ADC☆26Updated last year
- LMS-Adaptive Filter implement using verilog and Matlab☆47Updated 9 years ago
- Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)☆67Updated 7 years ago
- 通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结☆23Updated 6 years ago
- Pipeline FFT Implementation in Verilog HDL☆141Updated 6 years ago
- This project aims to implement a digital predistortion algorithm for power amplifier linearizion using vhdl. It contains VHDL design for …☆17Updated 2 years ago
- NMS_decode☆15Updated 5 years ago
- Wi-Fi LDPC codec Verilog IP core☆18Updated 6 years ago
- A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA☆179Updated last year
- Bilinear interpolation realizes image scaling based on FPGA☆29Updated 5 years ago
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 5 years ago
- asynchronous fifo based on verilog☆12Updated 3 years ago
- 本工程使用纯verilog编写rtl代码,在FPGA上搭建神经网络LeNet-5,实现手写数字识别的功能。☆32Updated 11 months ago
- Verilog module for calculation of FFT.☆186Updated 13 years ago
- ☆11Updated 7 years ago
- An AXI DDR3 SDRAM controller for FPGA☆41Updated last year
- ☆22Updated 3 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆56Updated 2 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆48Updated 6 years ago
- verilog☆21Updated 2 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆124Updated last year
- SPI interface connect to APB BUS with Verilog HDL☆37Updated 4 years ago
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago