Alternatives and similar repositories for cpu-cache-simulator

Users that are interested in cpu-cache-simulator are comparing it to the libraries listed below

• aakahlow / gem5Valid_Haswell
  ☆21Updated 5 years ago
• hadibrais / archsim
  A survey on architectural simulators focused on CPU caches.
  ☆16Updated 5 years ago
• melver / mc2lib
  Memory consistency model checking and test generation library.
  ☆15Updated 9 years ago
• darchr / gem5art
  Artifact, reproducibility, and testing utilites for gem5
  ☆23Updated 4 years ago
• gthparch / macsim
  A heterogeneous architecture timing model simulator.
  ☆173Updated 3 months ago
• stanford-mast / zsim
  A fast and scalable x86-64 multicore simulator
  ☆31Updated 4 years ago
• yousei-github / ChampSim-Ramulator
  A simulator integrates ChampSim and Ramulator.
  ☆19Updated 4 months ago
• ucb-bar / ccbench
  Memory System Microbenchmarks
  ☆65Updated 2 years ago
• hanhwi / SimPoint
  ☆17Updated 3 years ago
• masc-ucsc / esesc
  ESESC: A Fast Multicore Simulator
  ☆140Updated last month
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆46Updated 8 years ago
• CMU-SAFARI / BDICompression
  Source code for the Base-Delta-Immediate Compression Algorithm (described in the PACT 2012 paper by Pekhimenko et al. at http://users.ece…
  ☆28Updated 10 years ago
• blucia0a / MultiCacheSim
  A Coherent Multiprocessor Cache Simulator Based on the SuperESCalar Cache Model
  ☆28Updated 12 years ago
• ymanerka / rtlcheck
  RTLCheck
  ☆23Updated 7 years ago
• stephand / ptlsim
  Stable, non-KVM version of PTLsim.
  ☆29Updated 9 years ago
• sstsimulator / sst-tutorials
  Tutorial Material from the SST Team
  ☆25Updated 4 months ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆42Updated 2 years ago
• acsl-technion / ntl
  Networking Template Library for Vivado HLS
  ☆29Updated 5 years ago
• ctrippel / TriCheck
  ☆13Updated 8 years ago
• gem5-graphics / gem5-graphics
  gem5 simulator with a gpgpu+graphics GPU model
  ☆61Updated 5 years ago
• PrincetonUniversity / primesim
  A parallel and distributed simulator for thousand-core chips
  ☆27Updated 7 years ago
• umd-memsys / gem5
  This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…
  ☆13Updated 5 years ago
• fpgasystems / fpga-hyperloglog
  FPGA-based HyperLogLog Accelerator
  ☆12Updated 5 years ago
• aliireza / slice-aware
  Slice-aware Memory Management - Exploiting NUCA Characteristic of LLC in Intel Processors
  ☆41Updated 6 years ago
• SakalisC / Splash-3
  The Splash-3 benchmark suite
  ☆45Updated 2 years ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• daniellustig / riscv-memory-model
  A formalization of the RVWMO (RISC-V) memory model
  ☆35Updated 3 years ago
• efeslab / lapidary
  Creating beautiful gem5 simulations
  ☆49Updated 4 years ago
• CMU-SAFARI / Cache-Memory-Hog
  Cache and main memory hog programs. These are programs with specific access patterns to evict the already existing cache blocks of variou…
  ☆21Updated 9 years ago
• wangziqi2013 / zsim-base
  Base repo of a workable zsim on newer version of Ubuntu, with PIN-2.14 binary (the original zSim no longer works)
  ☆13Updated 3 years ago