ZyWCN1998 / MyDevEnvFileLinks
My Neovim & TMUX & Terminal setup on Ubuntu 22.04 LTS for C/C++/Verilog/System Verilog Development
☆16Updated last year
Alternatives and similar repositories for MyDevEnvFile
Users that are interested in MyDevEnvFile are comparing it to the libraries listed below
Sorting:
- Unofficial guide for ysyx students applying to ShanghaiTech University☆23Updated 11 months ago
- "aura" my super-scalar O3 cpu core☆25Updated last year
- The Scala parser to parse riscv/riscv-opcodes generate☆21Updated this week
- ☆92Updated 3 months ago
- ☆160Updated last month
- An exquisite superscalar RV32GC processor.☆165Updated last year
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆32Updated 9 months ago
- ☆66Updated last year
- ☆64Updated 3 years ago
- ☆19Updated 2 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆126Updated 3 years ago
- 使用 VSCode 舒适地开发 Verilog☆36Updated 5 years ago
- ☆70Updated 11 months ago
- Documentation for XiangShan Design☆40Updated last week
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆182Updated 4 years ago
- Verilog formatter☆199Updated 2 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆193Updated last year
- ☆36Updated 6 months ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆66Updated 3 years ago
- NJU Virtual Board☆297Updated 4 months ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆113Updated 3 years ago
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆73Updated 3 years ago
- ☆90Updated 2 months ago
- AXI协议规范中文翻译版☆171Updated 3 years ago
- ☆86Updated last month
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Updated 3 years ago
- Modern co-simulation framework for RISC-V CPUs☆170Updated this week
- LoveLonelyTime's RISC-V core basic version, RV32I, five pipeline stages.☆17Updated last year