Alternatives and similar repositories for MyDevEnvFile

Users that are interested in MyDevEnvFile are comparing it to the libraries listed below

• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• OSCPU / ysyxSoC
  ☆86Updated last month
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆21Updated 3 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated last month
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆120Updated 2 years ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 10 months ago
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆21Updated this week
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆62Updated 2 years ago
• OSCPU / yosys-sta
  ☆64Updated last month
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆73Updated 3 years ago
• BAO-Rongxin / Intelligent-BLDC-driver
  The project includes codes, specification, presentation and other information.
  ☆26Updated 4 years ago
• RainEggplant / vscode-verilog-integration
  使用 VSCode 舒适地开发 Verilog
  ☆32Updated 4 years ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆107Updated 2 years ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• puckbee / moli
  ☆14Updated this week
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆156Updated 4 months ago
• LoveLonelyTime / LLTRISC-V
  LoveLonelyTime's RISC-V core basic version, RV32I, five pipeline stages.
  ☆17Updated last year
• flyjancy / CortexM0_SoC_Task
  Step by step tutorial for building CortexM0 SoC
  ☆38Updated 3 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆40Updated last year
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• YSYX-OpenDoc / riscv-isa-manual
  ☆20Updated last week
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 4 years ago
• OSCPU / chisel-playground
  ☆67Updated 4 months ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆151Updated 2 years ago
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆23Updated last year
• zion-group / VerilogCodingStyle
  ☆63Updated 4 years ago
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆48Updated last year