Alternatives and similar repositories for MyDevEnvFile

Users that are interested in MyDevEnvFile are comparing it to the libraries listed below

• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆23Updated 11 months ago
• RainEggplant / vscode-verilog-integration
  使用 VSCode 舒适地开发 Verilog
  ☆36Updated 5 years ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated last year
• BAO-Rongxin / Intelligent-BLDC-driver
  The project includes codes, specification, presentation and other information.
  ☆26Updated last week
• Nitcloud / Digital-IDE
  在vscode上的数字设计开发插件
  ☆394Updated 3 years ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆32Updated 9 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆25Updated last year
• OSCPU / ysyx-workbench
  ☆161Updated last month
• OSCPU / ysyxSoC
  ☆92Updated 4 months ago
• ericsonj / verilog-format
  Verilog formatter
  ☆198Updated 2 years ago
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆165Updated last year
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆113Updated 3 years ago
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆22Updated 2 weeks ago
• zion-group / VerilogCodingStyle
  ☆65Updated 5 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆171Updated 3 years ago
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆126Updated 3 years ago
• loykylewong / FPGA-Application-Development-and-Simulation
  《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
  ☆134Updated last month
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆74Updated 3 years ago
• mperov / fixSegfaultVCS
  There is segmentation fault of VCS which should be fixed.
  ☆42Updated 2 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆194Updated last year
• OSCPU / yosys-sta
  ☆90Updated 2 months ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆151Updated last year
• OSCPU / chisel-playground
  ☆71Updated last week
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆76Updated 4 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆171Updated this week
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆24Updated last year
• CherrySprings / CherrySprings
  ☆19Updated 2 years ago
• YSYX-OpenDoc / riscv-isa-manual
  ☆21Updated 8 months ago
• lizhirui / DreamCore
  ☆64Updated 3 years ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆299Updated 5 months ago