hibioru / Student-Scores-Management-SystemView external linksLinks
一个学生成绩管理系统。
☆24Jul 2, 2020Updated 5 years ago
Alternatives and similar repositories for Student-Scores-Management-System
Users that are interested in Student-Scores-Management-System are comparing it to the libraries listed below
Sorting:
- Network on chip based neural network accelerator☆10Mar 25, 2021Updated 4 years ago
- LLM-DSE: Searching Accelerator Parameters with LLM Agents☆13May 22, 2025Updated 8 months ago
- Fork of the gem5 simulator with Garnet2.0 and DSENT extensions☆13Jan 28, 2019Updated 7 years ago
- Digital IC design and vlsi notes☆12Jun 24, 2020Updated 5 years ago
- ☆15Mar 24, 2023Updated 2 years ago
- ☆10Dec 28, 2020Updated 5 years ago
- ☆10Oct 8, 2021Updated 4 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- Little RISC-V 3-stage Pipeline CPU☆16Jun 14, 2021Updated 4 years ago
- 简单的代码控制系统☆13Oct 16, 2021Updated 4 years ago
- Netrace: a network packet trace reader☆14Jun 16, 2014Updated 11 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 3 years ago
- This repository contains the implementation of RISC-V Single Cycle Cores done by Undergraduate Students by using CHISEL and Functional Pr…☆10Oct 12, 2022Updated 3 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Updated this week
- RTL generator for SpGEMM☆10Feb 2, 2021Updated 5 years ago
- Contains all labs for EECS 251B for spring 2022☆12Mar 31, 2022Updated 3 years ago
- This repository is for students to go through the Learning Journey for CHISEL and Funcitonal Programming with SCALA also perform tasks re…☆15Sep 7, 2025Updated 5 months ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆17Feb 27, 2021Updated 4 years ago
- Official code for the paper "HEXA-MoE: Efficient and Heterogeneous-Aware MoE Acceleration with Zero Computation Redundancy"☆15Mar 6, 2025Updated 11 months ago
- RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)☆15Sep 5, 2019Updated 6 years ago
- A hardware accelerated IP packet forwarder running on programmable ICs☆15Jan 21, 2023Updated 3 years ago
- AIChip 2021 project, NCKU☆17May 6, 2021Updated 4 years ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆13Mar 5, 2017Updated 8 years ago
- 🎞️ NoC router in Verilog with FIFO☆16Sep 1, 2022Updated 3 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Jul 2, 2022Updated 3 years ago
- dlsite音声信息爬取,包括RJ号,标题,图片,声优,简介等,存为sqlite库☆15Nov 26, 2020Updated 5 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Nov 27, 2022Updated 3 years ago
- ☆23Nov 27, 2025Updated 2 months ago
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆23Jun 16, 2025Updated 7 months ago
- The open-source Mixture of Depths code and the official implementation of the paper "Router-Tuning: A Simple and Effective Approach for E…☆28Oct 1, 2025Updated 4 months ago
- Code repo for efficient quantized MoE inference with mixture of low-rank compensators☆31Apr 14, 2025Updated 10 months ago
- 国科大一生一芯第二期: RISCV-64 五级流水线CPU☆18Apr 17, 2021Updated 4 years ago
- course design☆23Feb 28, 2018Updated 7 years ago
- ☆18Dec 2, 2017Updated 8 years ago
- I am simply a Note☆21May 11, 2022Updated 3 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- ☆25Feb 11, 2025Updated last year