jackwadden / ANMLZoo
High-performance automata-processing engines are traditionally evaluated using a limited set of regular expression rulesets. While regular expression rulesets are valid real-world examples of use cases for automata processing, they represent a small proportion of all use cases for automata-based computing. With the recent availability of archit…
☆32Updated last year
Related projects ⓘ
Alternatives and complementary repositories for ANMLZoo
- VASim is a virtual homogeneous non-deterministic finite automata automata simulator and transformation tool. VASim can parse, transform, …☆35Updated 6 months ago
- Automata Benchmark Suite☆19Updated last year
- ☆23Updated 3 years ago
- ☆19Updated 2 years ago
- ☆18Updated 3 years ago
- Creating beautiful gem5 simulations☆45Updated 3 years ago
- ILA Model Database☆20Updated 4 years ago
- A Language for Closed-form High-level ARchitecture Modeling☆19Updated 4 years ago
- A high-level performance analysis tool for FPGA-based accelerators☆18Updated 7 years ago
- ColTraIn HBFP Training Emulator☆16Updated last year
- SST Architectural Simulation Components and Libraries☆92Updated last week
- Polyhedral High-Level Synthesis in MLIR☆29Updated last year
- ☆25Updated last month
- GenStore is the first in-storage processing system designed for genome sequence analysis that greatly reduces both data movement and comp…☆12Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆16Updated 2 years ago
- A fast and scalable x86-64 multicore simulator☆31Updated 3 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 2 months ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆47Updated 5 years ago
- The Splash-3 benchmark suite☆42Updated last year
- Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"☆27Updated 2 years ago
- ☆47Updated 5 years ago
- Alloy models for automatic synthesis of memory model litmus test suites (from ASPLOS 2017)☆15Updated 9 months ago
- Architect's workbench☆9Updated 8 years ago
- SMASH is a hardware-software cooperative mechanism that enables highly-efficient indexing and storage of sparse matrices. The key idea of…☆15Updated 4 years ago
- PIM-ML is a benchmark for training machine learning algorithms on the UPMEM architecture, which is the first publicly-available real-worl…☆18Updated last year
- Haystack is an analytical cache model that given a program computes the number of cache misses.☆42Updated 5 years ago
- ETHZ Heterogeneous Accelerated Compute Cluster.☆29Updated last month
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆19Updated 4 years ago
- A polyhedral compiler for hardware accelerators☆56Updated 3 months ago