Efficient Sampling of SAT Solutions for Testing
☆34Sep 20, 2019Updated 7 years ago
Alternatives and similar repositories for quicksampler
Users that are interested in quicksampler are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints☆30Sep 20, 2019Updated 7 years ago
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆14Mar 27, 2025Updated last year
- A prototype SMT-solver for the theory of bit-vectors and uninterpreted functions.☆10Dec 10, 2023Updated 2 years ago
- A Framework for Model-Backed Generators. Backend for AutoPandas (https://autopandas.io)☆21Sep 3, 2021Updated 5 years ago
- A mutation testing tool designed to work with large C++ (and C) codebases.☆15Oct 8, 2026Updated 3 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- GuidedSampler: Coverage-guided Sampling of SMT Solutions☆15Jul 9, 2025Updated last year
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 3 years ago
- Iodine: Verifying Constant-Time Execution of Hardware☆18Mar 29, 2021Updated 5 years ago
- Code for enumeration from a CFG☆20Sep 25, 2023Updated 3 years ago
- JReduce is a tool to reduce Java ByteCode☆13Oct 12, 2021Updated 5 years ago
- ☆33Sep 1, 2026Updated 2 months ago
- ☆10Sep 29, 2024Updated 2 years ago
- A tool to connect SMT-based frontends to Lean4.☆21Updated this week
- A collection of datapath circuit design and verification benchmarks☆19Aug 24, 2026Updated 2 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Project Repo for the Simulator Independent Coverage Research☆21Feb 28, 2023Updated 3 years ago
- ☆15Jun 18, 2023Updated 3 years ago
- A fork of Yosys that integrates the CellIFT pass☆14Sep 12, 2026Updated last month
- RTLCheck☆26Oct 9, 2018Updated 8 years ago
- A DSL and compiler for generating peephole optimizers for Cranelift☆64May 14, 2020Updated 6 years ago
- ☆29Mar 16, 2023Updated 3 years ago
- ☆32Nov 2, 2025Updated last year
- ☆11Jul 1, 2025Updated last year
- A library for verifying graph-manipulating programs. Powered by Coq and VST. Compatible with CompCert.☆21Updated this week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆17Jan 5, 2022Updated 4 years ago
- ☆12Jun 14, 2023Updated 3 years ago
- ☆20Jul 15, 2026Updated 3 months ago
- A Fast Floating-Point Satisfiability Solver☆31Jul 26, 2025Updated last year
- ☆15Feb 6, 2021Updated 5 years ago
- Symbolic Liveness Analysis of real-world software building upon KLEE to detect liveness violations (e.g. infinite loop bugs)☆12Dec 16, 2021Updated 4 years ago
- An automated theorem prover for intuitionistic propostional logic☆14Sep 21, 2020Updated 6 years ago
- Concolic analysis tool for Java☆21Jul 17, 2023Updated 3 years ago
- GPU kernel verification with Pulse☆27Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Parallel String Graph Construction, Transitive Reduction, and Contig Generation for De Novo Genome Assembly☆16Jun 11, 2024Updated 2 years ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Dec 1, 2018Updated 7 years ago
- ☆22Sep 28, 2022Updated 4 years ago
- bil verification tool☆12Jun 30, 2022Updated 4 years ago
- Some experiments with SMT solvers and GIMPLE IR☆83Updated this week
- C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.☆10Oct 21, 2020Updated 6 years ago
- Automatic generation of architecture-level models for hardware from its RTL design.☆17Apr 12, 2023Updated 3 years ago