freecores / bilinear_demosaic
Demosaic (Bilinear)
☆9Updated 10 years ago
Related projects ⓘ
Alternatives and complementary repositories for bilinear_demosaic
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆31Updated 5 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- ☆13Updated last year
- Verilog Code for a JPEG Decoder☆32Updated 6 years ago
- NoC based MPSoC☆10Updated 10 years ago
- APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS☆24Updated last year
- Reed Solomon Decoder (204,188)☆11Updated 10 years ago
- CORDIC VLSI-IP for deep learning activation functions☆13Updated 5 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 6 years ago
- Microshift Compression: An Efficient Image Compression Algorithm for Hardware☆32Updated 3 years ago
- MIPI CSI-2 RX☆29Updated 3 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆20Updated 5 years ago
- Pipelined FFT/IFFT 64 points processor☆11Updated 10 years ago
- 基于FPGA的FFT☆12Updated 5 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆41Updated 2 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆25Updated 10 months ago
- mirror of https://git.elphel.com/Elphel/eddr3☆39Updated 7 years ago
- IP operations in verilog (simulation and implementation on ice40)☆52Updated 5 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆14Updated 3 months ago
- Completed LDO Design for Skywaters 130nm☆14Updated last year
- FPGA和USB3.0桥片实现USB3.0通信☆54Updated 2 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆38Updated 4 months ago
- USB2.0 Verilog☆15Updated 5 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆17Updated 6 years ago
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆31Updated last year
- minimal code to access ps DDR from PL☆19Updated 5 years ago
- SPI-Flash XIP Interface (Verilog)☆35Updated 3 years ago
- This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.☆22Updated last year