freand76 / digsim
An interactive digital logic simulator with verilog support (Yosys)
☆19Updated 2 months ago
Alternatives and similar repositories for digsim:
Users that are interested in digsim are comparing it to the libraries listed below
- Co-simulation and behavioural verification with VHDL, C/C++ and Python/m☆13Updated this week
- FPGA Development toolset☆20Updated 7 years ago
- Custom 64-bit pipelined RISC processor☆18Updated 9 months ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- A low-level hierarchical netlist assembler for FPGAs☆11Updated 3 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆26Updated 4 years ago
- ulx3s ghdl examples☆14Updated 4 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- IRSIM switch-level simulator for digital circuits☆32Updated 2 weeks ago
- Digital Circuit rendering engine☆38Updated last year
- A bit-serial CPU☆18Updated 5 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated 2 weeks ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆32Updated this week
- This repository contain source code for ngspice and ghdl integration☆30Updated 3 months ago
- Circuit simulator of the Qucs project☆28Updated 3 months ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15Updated 6 years ago
- fasmg implementation of ARMv6-M instruction set☆11Updated last year
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆12Updated 2 months ago
- CLIp is a clipboard manager for a command line interface written in 100% standard C only. Pipe to it to copy, pipe from it to paste.☆14Updated 3 years ago
- Notes, scripts and apps to quickfeather board☆10Updated 3 years ago
- Unencrypted, UDP-based alternative to the Gemini protocol☆16Updated 7 months ago
- A small and simple rv32i core written in Verilog☆13Updated 2 years ago
- A design for TinyTapeout☆16Updated 2 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆16Updated 2 years ago
- VHDL grammar for tree-sitter☆31Updated last year
- A set of helpers to implement a text user interface (TUI) in a terminal.☆12Updated 2 years ago
- Open source hardware down to the chip level!☆30Updated 3 years ago
- betrusted.io main SoC design☆12Updated 5 years ago
- Unofficial nextpnr WebAssembly packages☆16Updated last week
- Alliance VLSI CAD Tools (LIP6)☆13Updated 2 months ago