Alternatives and similar repositories for digsim

Users that are interested in digsim are comparing it to the libraries listed below

• FOSSEE / nghdl
  This repository contain source code for ngspice and ghdl integration
  ☆34Updated last year
• olofk / qerv
  ☆20Updated 9 months ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆35Updated 2 months ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated 3 weeks ago
• drom / logidrom
  Digital Circuit rendering engine
  ☆39Updated 6 months ago
• gnucap / gnucap
  gnucap mirror (read only)
  ☆31Updated this week
• veripool / dinotrace
  Simulation VCD waveform viewer, using old Motif UI
  ☆28Updated 2 years ago
• RTimothyEdwards / XCircuit
  XCircuit circuit drawing and schematic capture tool
  ☆138Updated 2 months ago
• VHDPlus / VHDPlus_Libraries_and_Examples
  This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…
  ☆20Updated last year
• CospanDesign / nysa
  FPGA Development toolset
  ☆20Updated 8 years ago
• EEVengers / libtslitex
  This is a C library to interface with the LiteX Firmware on Thunderscope over PCIe
  ☆11Updated 3 weeks ago
• wavedrom / verilog
  wavedrom to verilog converter
  ☆17Updated 4 years ago
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆28Updated 3 weeks ago
• apertus-open-source-cinema / axiom-micro-mainboard
  axiom micro mainboard containing the cmos sensor, headers for plugin modules and more
  ☆40Updated 5 years ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆33Updated 5 years ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆79Updated 3 years ago
• suarezvictor / litex_imgui_usb_demo
  Soft USB for LiteX
  ☆50Updated 4 months ago
• lnls-dig / general-cores
  general-cores
  ☆21Updated 6 months ago
• mattvenn / vga_clock_pcb
  Open source hardware down to the chip level!
  ☆30Updated 4 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆24Updated 4 years ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆77Updated last week
• umarcor / hwstudio
  GUI editor for hardware description designs
  ☆30Updated 2 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆20Updated 3 years ago
• Nic30 / sphinx-hwt
  Sphinx extension for visual documentation of hardware written in HWT
  ☆11Updated 2 months ago
• EvgenyMuryshkin / qusoc
  QuSoC demo projects and template
  ☆24Updated last year
• tongchen126 / fpga_pcie_ethernet
  ☆17Updated 3 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 4 years ago
• cclienti / wavedisp
  Python classes to create agnostic wave files for HDL simulator viewer
  ☆12Updated 5 years ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆60Updated last week
• OSVVM / UART
  OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verificati…
  ☆13Updated last month