An interactive digital logic simulator with verilog support (Yosys)
☆28Mar 9, 2026Updated last week
Alternatives and similar repositories for digsim
Users that are interested in digsim are comparing it to the libraries listed below
Sorting:
- Repo to help explain the different options users have for packaging.☆19Jun 8, 2022Updated 3 years ago
- An embeddable FPGA SoM designed for high-speed audio and USB applications.☆26Mar 9, 2026Updated last week
- GSI Timing Gateware and Tools☆14Updated this week
- Experimental Lattice ECP5-driven Data Center Security Communication Module☆20Jul 22, 2024Updated last year
- Artix7 SOM☆18Sep 9, 2024Updated last year
- Python library for operations with VCD and other digital wave files☆55Nov 12, 2025Updated 4 months ago
- fork of python-jenkins for https://review.openstack.org/460363☆12Apr 27, 2017Updated 8 years ago
- The first large scale formally verified reasoning dataset for Verilog☆21May 16, 2025Updated 10 months ago
- ☆12Mar 10, 2024Updated 2 years ago
- FPGA code for NeTV2☆16Dec 3, 2018Updated 7 years ago
- This project attempts to classify the entries in the Microsoft Malware Classification Challenge dataset using random forests.☆11Dec 22, 2016Updated 9 years ago
- PSSGen: Portable Test and Stimulus Standard DSL Generator☆14Dec 29, 2025Updated 2 months ago
- ☆17Apr 7, 2022Updated 3 years ago
- Open Source HVS for geiger counters.☆11Jan 20, 2026Updated 2 months ago
- nMigen examples for the ULX3S board☆12May 5, 2022Updated 3 years ago
- LiteX LUNA USB stack integration☆14Jun 12, 2022Updated 3 years ago
- hanLP-python server api☆12Apr 25, 2017Updated 8 years ago
- Pomodoro Timer for M5Stack Core Ink device☆11Jun 6, 2021Updated 4 years ago
- Characterizing and Optimizing EDA Flows for the Cloud (DATE'2021 and TCAD)☆11Nov 2, 2021Updated 4 years ago
- general-cores☆21Jul 16, 2025Updated 8 months ago
- Official implementation.☆27Jul 1, 2025Updated 8 months ago
- LiteX project for the ButterStick bootloader☆14Mar 13, 2023Updated 3 years ago
- ☆10Oct 23, 2016Updated 9 years ago
- The source codes of GRU model for Chinese poetry generation (CCL 2017).☆14Jul 9, 2019Updated 6 years ago
- ☆14Nov 28, 2024Updated last year
- ☆12May 21, 2024Updated last year
- Python bindings for coreir☆11Sep 13, 2023Updated 2 years ago
- UVM testbench for verifying the Pulpino SoC☆12Mar 23, 2020Updated 5 years ago
- Audio libs for load and play some audio files☆10Jan 3, 2021Updated 5 years ago
- Open-source IPs Package Manager (IPM)☆16Feb 24, 2025Updated last year
- 轻量级终端打串口日志工具,代替MobaXterm、SecureCRT、PuTTy,直接用Windows Terminal控制。 Serialport terminal tool☆23Feb 5, 2026Updated last month
- Main repository for DIVE☆17Feb 25, 2022Updated 4 years ago
- ☆14Mar 13, 2026Updated last week
- Hardware design for modular CNC controller☆15May 13, 2025Updated 10 months ago
- EDA Tools: Xilinx ISE 14.7 Dockerfile☆20Jun 20, 2022Updated 3 years ago
- Awesome projects using the Amaranth HDL☆20Feb 6, 2025Updated last year
- Audio DSP on an FPGA using eurorack-pmod + LiteX with firmware in Rust.☆17Oct 7, 2025Updated 5 months ago
- A less cramped XMOS xCORE200 Platform based DSP and microcontroller PCB design - open source hardware☆13Apr 4, 2019Updated 6 years ago
- Simple Video to audio Converter☆12Aug 14, 2024Updated last year