freand76 / digsimLinks
An interactive digital logic simulator with verilog support (Yosys)
☆27Updated 3 weeks ago
Alternatives and similar repositories for digsim
Users that are interested in digsim are comparing it to the libraries listed below
Sorting:
- This repository contain source code for ngspice and ghdl integration☆33Updated last year
- ☆20Updated 8 months ago
- IRSIM switch-level simulator for digital circuits☆35Updated 2 months ago
- QuSoC demo projects and template☆24Updated last year
- Simulation VCD waveform viewer, using old Motif UI☆28Updated 2 years ago
- This is a C library to interface with the LiteX Firmware on Thunderscope over PCIe☆11Updated 2 weeks ago
- Soft USB for LiteX☆50Updated 3 months ago
- FPGA Development toolset☆20Updated 8 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 weeks ago
- wavedrom to verilog converter☆17Updated 4 years ago
- Digital Circuit rendering engine☆39Updated 6 months ago
- ulx3s ghdl examples☆15Updated 4 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 4 years ago
- LiteX based FPGA gateware for Thunderscope.☆29Updated 3 weeks ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 4 years ago
- A graphical editor and event-driven simulator for digital circuits☆30Updated 3 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆77Updated this week
- GSI Timing Gateware and Tools☆14Updated last week
- Python classes to create agnostic wave files for HDL simulator viewer☆12Updated 5 years ago
- This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…☆20Updated last year
- XCircuit circuit drawing and schematic capture tool☆137Updated 2 months ago
- Open source hardware down to the chip level!☆30Updated 4 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Updated 2 years ago
- This repository contains sample code integrating Renode with Verilator☆26Updated 8 months ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Updated 3 years ago
- Bit streams forthe Ulx3s ECP5 device☆18Updated 2 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆27Updated 2 weeks ago
- ☆38Updated last month
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆31Updated 5 years ago
- gnucap mirror (read only)☆31Updated last week