Alternatives and similar repositories for digsim

Users that are interested in digsim are comparing it to the libraries listed below

• FOSSEE / nghdl
  This repository contain source code for ngspice and ghdl integration
  ☆33Updated 11 months ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆35Updated last month
• CospanDesign / nysa
  FPGA Development toolset
  ☆20Updated 8 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated 2 months ago
• drom / logidrom
  Digital Circuit rendering engine
  ☆39Updated 4 months ago
• EvgenyMuryshkin / qusoc
  QuSoC demo projects and template
  ☆23Updated last year
• veripool / dinotrace
  Simulation VCD waveform viewer, using old Motif UI
  ☆27Updated 2 years ago
• RTimothyEdwards / XCircuit
  XCircuit circuit drawing and schematic capture tool
  ☆131Updated last month
• kost / ulx3s-ghdl-examples
  ulx3s ghdl examples
  ☆14Updated 4 years ago
• EEVengers / libtslitex
  This is a C library to interface with the LiteX Firmware on Thunderscope over PCIe
  ☆11Updated this week
• olofk / qerv
  ☆19Updated 7 months ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆23Updated 4 years ago
• libresilicon / qtflow
  Free open source EDA tools
  ☆66Updated 6 years ago
• GSI-CS-CO / bel_projects
  GSI Timing Gateware and Tools
  ☆14Updated this week
• suarezvictor / litex_imgui_usb_demo
  Soft USB for LiteX
  ☆50Updated 2 months ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆63Updated 2 years ago
• PythonLinks / awesome-risc-v-soft-cores
  Compares the different RISC-V soft cores in order to help you select the best one for your application.
  ☆13Updated 6 months ago
• gnucap / gnucap
  gnucap mirror (read only)
  ☆29Updated 3 weeks ago
• apertus-open-source-cinema / axiom-micro-mainboard
  axiom micro mainboard containing the cmos sensor, headers for plugin modules and more
  ☆40Updated 4 years ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆78Updated 3 years ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆25Updated 3 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 4 years ago
• Nic30 / sphinx-hwt
  Sphinx extension for visual documentation of hardware written in HWT
  ☆11Updated last month
• TinyTapeout / tinytapeout-03
  ☆16Updated last year
• PandABlocks / PandABlocks-FPGA
  VHDL functional blocks with their simulations and test sequences
  ☆20Updated this week
• VHDPlus / VHDPlus_Libraries_and_Examples
  This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…
  ☆20Updated last year
• OSVVM / UART
  OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verificati…
  ☆13Updated 2 months ago
• rochus-keller / QtcVerilog
  This is a stand-alone Verilog IDE derived from a QtCreator 3.6.1 subset featuring the VerilogCreator plugin
  ☆21Updated 3 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆31Updated 3 years ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆59Updated 3 weeks ago