Alternatives and similar repositories for tlbdr

Users that are interested in tlbdr are comparing it to the libraries listed below

• cgvwzq / cachequery
  HW interface for memory caches
  ☆28Updated 5 years ago
• flowyroll / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆21Updated 4 years ago
• CPU-THU / Spectre-V4-ng
  The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Specula…
  ☆22Updated last year
• flowyroll / uarchsec
  ☆45Updated 6 years ago
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆20Updated 4 years ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 4 months ago
• FPSG-UIUC / Peek-a-Walk
  Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"
  ☆24Updated last week
• MATCHA-MIT / Pensieve
  This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.
  ☆23Updated last year
• libtea / frameworks
  Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser
  ☆61Updated 2 years ago
• miaochenlu / arch_sec_papers
  ☆15Updated 3 months ago
• bu-icsg / PHMon
  This repository contains the hardware, software, and OS support for the Programmable Hardware Monitor (PHMon).
  ☆26Updated 4 years ago
• vernamlab / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆21Updated 4 years ago
• mjyan0720 / InvisiSpec-1.0
  Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.
  ☆60Updated 5 years ago
• compsec-snu / specdoctor
  ☆25Updated 2 years ago
• FxPiGaAo / Hacky-Racer
  ☆17Updated 2 weeks ago
• cispa / BranchDifferent
  Implementation for the DIMVA'22 paper "Branch Different - Spectre Attacks on Apple Silicon"
  ☆32Updated 2 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆25Updated 2 weeks ago
• renxida / iseedeaduops-poc
  Proof-of-concept for I See Dead Micro-Ops transient execution attack
  ☆14Updated 3 years ago
• mktrm / SecSMT_Artifact
  The artifact for SecSMT paper -- Usenix Security 2022
  ☆27Updated 2 years ago
• isec-tugraz / halfdouble
  ☆16Updated 2 years ago
• cgvwzq / evsets
  Tool for testing and finding minimal eviction sets
  ☆104Updated 4 years ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆69Updated 3 months ago
• gururaj-s / mirage
  MIRAGE (USENIX Security 2021)
  ☆13Updated last year
• Miro-H / CacheSC
  Library for Prime+Probe cache side-channel attacks on L1 and L2
  ☆34Updated 5 years ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆15Updated 4 years ago
• ECLab-ITU / Cache-Side-Channel-Attacks
  This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.
  ☆52Updated 5 years ago
• yshalabi / covert-channel-tutorial
  Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…
  ☆48Updated 6 years ago
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆17Updated 4 years ago
• FPSG-UIUC / augury
  Using Data Memory-Dependent Prefetchers to Leak Data at Rest
  ☆36Updated 2 years ago
• FPSG-UIUC / Pandora
  Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture can Leak Private Data
  ☆21Updated 2 years ago