Alternatives and similar repositories for DiffTune

Users that are interested in DiffTune are comparing it to the libraries listed below

• SwarmArch / T4
  Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"
  ☆28Updated 3 years ago
• cornell-zhang / datuner
  DATuner Repository
  ☆17Updated 7 years ago
• kumasento / polsca
  Polyhedral High-Level Synthesis in MLIR
  ☆35Updated 2 years ago
• melver / mc2lib
  Memory consistency model checking and test generation library.
  ☆16Updated 9 years ago
• CMU-SAFARI / CROW
  Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …
  ☆15Updated 6 years ago
• he-actlab / polymath
  ☆22Updated 11 months ago
• sfu-arch / needle
  ☆13Updated 3 years ago
• intel / neuro-vectorizer
  NeuroVectorizer is a framework that uses deep reinforcement learning (RL) to predict optimal vectorization compiler pragmas for for loops…
  ☆98Updated 3 years ago
• ymanerka / rtlcheck
  RTLCheck
  ☆24Updated 7 years ago
• ucb-bar / autophase
  ☆35Updated 4 years ago
• UCSBarchlab / Charm
  A Language for Closed-form High-level ARchitecture Modeling
  ☆21Updated 5 years ago
• baco-authors / baco
  ☆17Updated 2 years ago
• mit-plv / hemiola
  A Coq framework to support structural design and proof of hardware cache-coherence protocols
  ☆14Updated 3 years ago
• efeslab / lapidary
  Creating beautiful gem5 simulations
  ☆49Updated 4 years ago
• CMU-SAFARI / BEER
  BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are use…
  ☆19Updated 5 years ago
• UCLA-SEAL / HeteroGen
  HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)
  ☆17Updated last year
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆24Updated 5 years ago
• jianyicheng / iiProver
  An LLVM pass to prove that an II works for the given loop for Vitis HLS
  ☆11Updated 4 years ago
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 4 years ago
• hadibrais / archsim
  A survey on architectural simulators focused on CPU caches.
  ☆16Updated 5 years ago
• jetafese / btor2mlir
  Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification
  ☆20Updated 4 months ago
• yaohsiaopid / rtl2uspec
  ☆11Updated 7 months ago
• aakahlow / gem5Valid_Haswell
  ☆21Updated 5 years ago
• sfu-arch / muir
  ☆24Updated 5 years ago
• zhguanw / lin-analyzer
  A high-level performance analysis tool for FPGA-based accelerators
  ☆19Updated 8 years ago
• daniellustig / pipecheck
  ☆19Updated 11 years ago
• milo168 / FPGA25_SAT_Accel
  FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository
  ☆13Updated 10 months ago
• UCSBarchlab / owl
  Control Logic Synthesis: Drawing the Rest of the OWL
  ☆13Updated last year
• sstsimulator / sst-tutorials
  Tutorial Material from the SST Team
  ☆25Updated 5 months ago
• SakalisC / Splash-3
  The Splash-3 benchmark suite
  ☆45Updated 2 years ago