ithemal / DiffTuneLinks
☆18Updated 3 years ago
Alternatives and similar repositories for DiffTune
Users that are interested in DiffTune are comparing it to the libraries listed below
Sorting:
- Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"☆29Updated 3 years ago
- ☆33Updated 3 years ago
- NeuroVectorizer is a framework that uses deep reinforcement learning (RL) to predict optimal vectorization compiler pragmas for for loops…☆95Updated 2 years ago
- FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository☆13Updated 4 months ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆24Updated 8 months ago
- ☆11Updated last month
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆17Updated 10 months ago
- ☆21Updated 2 years ago
- A list of benchmark suites used in the research related to compilers, program performance, scientific computations etc.☆53Updated last year
- Base repo of a workable zsim on newer version of Ubuntu, with PIN-2.14 binary (the original zSim no longer works)☆13Updated 2 years ago
- Memory consistency model checking and test generation library.☆15Updated 8 years ago
- RTLCheck☆22Updated 6 years ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆15Updated 8 months ago
- ☆17Updated last year
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- DATuner Repository☆18Updated 6 years ago
- ☆14Updated 3 years ago
- A Language for Closed-form High-level ARchitecture Modeling☆21Updated 5 years ago
- A Generic Distributed Auto-Tuning Infrastructure☆22Updated 4 years ago
- Polyhedral High-Level Synthesis in MLIR☆33Updated 2 years ago
- ☆36Updated 6 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 6 years ago
- Automatic generation of architecture-level models for hardware from its RTL design.☆13Updated 2 years ago
- Artifact, reproducibility, and testing utilites for gem5☆22Updated 4 years ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆31Updated last year
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- ☆21Updated 5 months ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14Updated 3 years ago
- Creating beautiful gem5 simulations☆49Updated 4 years ago
- ☆15Updated 5 years ago