efeacer / PongGameVHDLLinks
Here is the code of my digital design term project, which is an implementation of the classic arcade game Pong in VGA using basys3 board. The game is implemented using VHDL hardware description language. You can find a video description from the link: https://www.youtube.com/watch?v=LqOlgilpCYc&t=36s
☆6Updated 7 years ago
Alternatives and similar repositories for PongGameVHDL
Users that are interested in PongGameVHDL are comparing it to the libraries listed below
Sorting:
- Verilog HDL files☆144Updated last year
- This repository contains all labs done as a part of the Embedded Logic and Design course.☆23Updated 7 years ago
- Practices related to the fundamental level of the programming language Verilog.☆11Updated 2 years ago
- VHDL course at Brno University of Technology☆113Updated last month
- "Mehmet Burak Aykenar" YouTube kanalında yayınlanan VHDL ve FPGA dersleri ile ilgili kodları içermektedir.☆103Updated last year
- Straightforward Pong Game written in VHDL. Scoring and Multiplayer☆20Updated 9 years ago
- FPGA Design of a Neural Network for Color Detection☆76Updated 4 months ago
- Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..☆38Updated 6 years ago
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆57Updated 2 years ago
- ECE 3300 HDL Code☆46Updated 2 years ago
- ☆95Updated 3 years ago
- A 2D convolution hardware implementation written in Verilog☆46Updated 4 years ago
- Pipeline FFT Implementation in Verilog HDL☆120Updated 6 years ago
- Implementing Different Adder Structures in Verilog☆70Updated 5 years ago
- Verilog for ASIC Design☆28Updated 3 years ago
- Basic UART TX/RX module for FPGA☆31Updated 6 years ago
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆128Updated 5 years ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆110Updated 3 years ago
- Pong game on an FPGA in Verilog.☆57Updated 13 years ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆50Updated 7 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆101Updated 2 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆54Updated last year
- Image Processing Toolbox in Verilog using Basys3 FPGA☆203Updated last month
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆130Updated last year
- Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)☆34Updated 2 months ago
- ☆12Updated 7 months ago
- ☆94Updated last year
- Senior Design Project at UW-Madison ECE☆15Updated 2 years ago
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆64Updated 3 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆96Updated last year