Alternatives and similar repositories for rv8-bench

Users that are interested in rv8-bench are comparing it to the libraries listed below

• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆25Updated 3 weeks ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 6 years ago
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆17Updated 4 years ago
• ilebedev / sanctum
  The MIT Sanctum processor top-level project
  ☆30Updated 5 years ago
• mjyan0720 / InvisiSpec-1.0
  Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.
  ☆60Updated 5 years ago
• riscv-admin / iopmp
  Group administration repository for Tech: IOPMP Task Group
  ☆13Updated 6 months ago
• cwfletcher / stt
  ☆35Updated 4 years ago
• Penglai-Enclave / Penglai-Enclave
  This is the main repo for Penglai.
  ☆69Updated last year
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆64Updated 5 years ago
• compsec-snu / specdoctor
  ☆25Updated 2 years ago
• CSL-KU / SpectreGuard
  Data-centric defense mechanism against Spectre attacks. (DAC'19)
  ☆11Updated 5 years ago
• renxida / iseedeaduops-poc
  Proof-of-concept for I See Dead Micro-Ops transient execution attack
  ☆14Updated 3 years ago
• Penglai-Enclave / Penglai-Enclave-TVM
  The main repo of Penglai Enclave based on RISC-V Trapped Virtual Memory (TVM).
  ☆40Updated 2 years ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 4 months ago
• riscvarchive / security
  RISC-V Security HC admin repo
  ☆18Updated 6 months ago
• Compass-All / Raft
  Hardware-assisted Dynamic Information Flow Tracking for Runtime Protection on RISC-V
  ☆10Updated last year
• MoeinGhaniyoun / TEESec
  TEESec: Pre-Silicon Vulnerability Discovery for Trusted Execution Environments
  ☆10Updated last year
• MATCHA-MIT / Pensieve
  This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.
  ☆23Updated last year
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆15Updated 4 years ago
• mktrm / SecSMT_Artifact
  The artifact for SecSMT paper -- Usenix Security 2022
  ☆27Updated 2 years ago
• riscv / riscv-spmp
  The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…
  ☆18Updated 2 weeks ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆69Updated 3 months ago
• riscvarchive / riscv-tee
  ☆38Updated 2 years ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆40Updated last year
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆20Updated 4 years ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆21Updated 2 years ago
• riscv-admin / trusted-computing
  ☆22Updated 2 years ago
• jasonyu1996 / elasticlave
  ☆23Updated 4 months ago
• ccelio / Speckle
  A wrapper for the SPEC CPU2006 benchmark suite.
  ☆88Updated 4 years ago
• efeslab / lapidary
  Creating beautiful gem5 simulations
  ☆49Updated 4 years ago