byuccl / coastLinks
Compiler Assisted Software Fault Tolerance
☆23Updated 4 years ago
Alternatives and similar repositories for coast
Users that are interested in coast are comparing it to the libraries listed below
Sorting:
- A set of benchmarks chosen to show the energy consumption of embedded devices under different conditions☆68Updated 2 years ago
- Testing processors with Random Instruction Generation☆44Updated last month
- Fuzzing for SpinalHDL☆16Updated 2 years ago
- A Modular Open-Source Hardware Fuzzing Framework☆34Updated 3 years ago
- Open Source AES☆31Updated last year
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆25Updated last year
- Fiber-based SystemVerilog Simulator.☆25Updated 3 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆34Updated 10 years ago
- RTLCheck☆22Updated 6 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆110Updated 2 months ago
- rfuzz: coverage-directed fuzzing for RTL research platform☆108Updated 3 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Xilinx Unisim Library in Verilog☆82Updated 5 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated last week
- FastPath_MP: An FPGA-based multi-path architecture for direct access from FPGA to NVMe SSD☆35Updated 4 years ago
- An LLVM based mini-C to Verilog High-level Synthesis tool☆37Updated 5 months ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- RISC-V vector extension ISA simulation☆16Updated 6 years ago
- C++17 implementation of an AST for Verilog code generation☆24Updated 2 years ago
- CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform☆11Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆32Updated last week
- COATCheck☆13Updated 6 years ago
- Code repository for Coppelia tool☆23Updated 4 years ago
- A time-predictable processor for mixed-criticality systems☆59Updated 9 months ago
- Pulp virtual platform☆23Updated 3 weeks ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- A powerful and modern open-source architecture description language.☆42Updated 7 years ago
- Qbox☆58Updated last week
- ☆64Updated 3 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago