alfikpl / aoR3000
The aoR3000 is a MIPS R3000A compatible core capable of booting the Linux kernel version 3.16 in about 3 seconds and with a rating of 48.74 BogoMIPS. It features a compatible MMU, but no FPU.
☆42Updated 10 years ago
Alternatives and similar repositories for aoR3000:
Users that are interested in aoR3000 are comparing it to the libraries listed below
- IBM PC Compatible SoC for a commercially available FPGA board☆68Updated 8 years ago
- OpenGL-like graphics pipeline on a Xilinx FPGA☆32Updated 14 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- LatticeMico32 soft processor☆104Updated 10 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆68Updated 2 years ago
- The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.☆76Updated 13 years ago
- HDMI core in Chisel HDL☆49Updated last year
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆30Updated 8 years ago
- Reverse engineering the XC2064 FPGA☆74Updated 3 years ago
- An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)☆72Updated 12 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆61Updated 6 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated last year
- Wishbone interconnect utilities☆38Updated last month
- Tools for FPGA development.☆44Updated last year
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆51Updated last year
- FPGA GPU design for DE1-SoC☆73Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆88Updated 4 years ago
- A wishbone controlled scope for FPGA's☆77Updated last year
- A single-wire bi-directional chip-to-chip interface for FPGAs☆116Updated 8 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 5 years ago
- MR1 formally verified RISC-V CPU☆54Updated 6 years ago
- A FPGA core for a simple SDRAM controller.☆117Updated 3 years ago
- Project X-Ray Database: XC7 Series☆65Updated 3 years ago
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆76Updated 4 years ago
- ☆28Updated 8 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆62Updated 6 years ago
- Open Processor Architecture☆26Updated 8 years ago
- Another tiny RISC-V implementation☆54Updated 3 years ago