Firmware IRIG-B decoder
☆33Dec 14, 2022Updated 3 years ago
Alternatives and similar repositories for irig-decoder
Users that are interested in irig-decoder are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Global Positioning System (GPS) Disciplined Oscillator (DO)☆16Jan 3, 2021Updated 5 years ago
- port "gps sdr sim" to widnows and make it easy to use☆15Oct 2, 2025Updated last year
- HDL & FPGA 学习和规范。CC-BY-NC-SA 4.0。☆15Jun 9, 2023Updated 3 years ago
- Energy-Efficient Power and Subcarrier Allocation for OFDMA Systems with Value Function Approximation Approach. EI paper from march to sep…☆13Mar 13, 2017Updated 9 years ago
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆11Feb 28, 2015Updated 11 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Next-Generation FPGA Place-and-Route☆10Aug 1, 2018Updated 8 years ago
- Using Software Designed Radio to transmit & receive FM signal☆49Apr 2, 2018Updated 8 years ago
- Used for hardware trojan detection(Based on Trust_Hub)☆10Jul 30, 2019Updated 7 years ago
- FreeRTOS v9.0.0 configured for a STM32F103VC (VCT6)☆16Apr 27, 2020Updated 6 years ago
- ☆20Jul 29, 2025Updated last year
- ☆33Jun 16, 2024Updated 2 years ago
- Verilog Implementation of SM4 s-box☆22Jun 24, 2019Updated 7 years ago
- 8b10b Encoder/Decoder☆13Jul 17, 2014Updated 12 years ago
- 51单片机控制的智能小车☆13Feb 23, 2016Updated 10 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Verilog CAN controller that is compatible to the SJA 1000.☆20Apr 17, 2021Updated 5 years ago
- tang-nano-4K mini samples☆15Feb 1, 2022Updated 4 years ago
- ☆27Mar 25, 2019Updated 7 years ago
- Implementation of the SHA256 Algorithm in Verilog☆39Jan 2, 2012Updated 14 years ago
- CRC Theory and Implement. explain initial value of CRC☆16Feb 26, 2021Updated 5 years ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Dec 1, 2018Updated 7 years ago
- SRT (Secure Reliable Transport) Swift wrapper☆15Sep 7, 2022Updated 4 years ago
- Various utilities for working with FPGAs☆13Mar 30, 2016Updated 10 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆26Dec 21, 2025Updated 9 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Mux h.264 raw stream to TS based on FFmpeg.☆14Nov 18, 2014Updated 11 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆37Updated this week
- Parallel Redundancy Protocol (PRP version 1) software implementation☆14Apr 28, 2021Updated 5 years ago
- 常用Verilog模块☆22Mar 3, 2020Updated 6 years ago
- Hardware Security Labs☆31May 3, 2017Updated 9 years ago
- 简易的flash模拟eeprom程序,支持磨损平衡,支持掉电安全☆16Dec 22, 2021Updated 4 years ago
- This repository contain source code for ngspice and ghdl integration☆37Jun 3, 2026Updated 4 months ago
- Generate UVM testbench framework template files with Python 3☆26Dec 23, 2019Updated 6 years ago
- Standalone application based on ADI hdl and no_OS for ANTSDR.☆29Mar 27, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Android 投屏到电脑上,类似vysor。不需要网连数据线,延时小。原理是电脑上布一个socket.io服务器;手机通过socket.io连接到自己布置的局域网服务器,然后通过ImageRedaer不断截屏,将画片发送到局域网服务器。最后一步就是电脑的显示,服务器上获得…☆25Dec 31, 2019Updated 6 years ago
- Yet Another VHDL tool☆30May 15, 2017Updated 9 years ago
- include hdlc (miao), 422 grapher, 1553b☆21Oct 10, 2019Updated 7 years ago
- development interface mil-std-1553b for system on chip☆26Feb 2, 2018Updated 8 years ago
- Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)☆37Jun 30, 2024Updated 2 years ago
- 暂无描述☆31Oct 4, 2026Updated last week
- SDIO Device Verilog Core☆25Jul 25, 2018Updated 8 years ago