Alternatives and similar repositories for Behavior-modeling-of-PLL

Users that are interested in Behavior-modeling-of-PLL are comparing it to the libraries listed below

• UAH-IC-Design-Team / sky130-10-bit-SAR-ADC
  A 10bit SAR ADC in Sky130
  ☆25Updated 3 years ago
• shalan / Awesome-Sky130-IPs
  ☆14Updated 2 years ago
• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆26Updated 6 years ago
• muhammadaldacher / Analog-Design-of-1.9-GHz-PLL-system
  This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…
  ☆80Updated 2 years ago
• rnunes2311 / SAR_ADC_12bit
  12 bit SAR ADC IP in Skywater 130 nm PDK
  ☆20Updated last year
• maxs-well / LMS-sound-filtering-by-Verilog
  LMS sound filtering by Verilog
  ☆43Updated 5 years ago
• muhammadaldacher / Analog-Design-of-1.5-bit-Pipeline-ADC-And-Boosted-OpAmp
  This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.
  ☆37Updated 3 years ago
• JoshuaEbenezer / FFT-cordic-HDL
  FFT implementation using CORDIC algorithm written in Verilog.
  ☆34Updated 7 years ago
• Starrynightzyq / Delta-Sigma-Modulator
  Delta-Sigma modulator (DSM) for fractional phase locked loop.
  ☆33Updated 4 years ago
• hpretl / python-deltasigma
  A port of the MATLAB Delta Sigma Toolbox based on free software and very little sleep
  ☆13Updated 3 years ago
• w32agobot / SKY130_SAR-ADC
  Fully-differential asynchronous non-binary 12-bit SAR-ADC
  ☆36Updated 2 years ago
• DexWen / LMS-Adaptive-filter
  LMS-Adaptive Filter implement using verilog and Matlab
  ☆48Updated 9 years ago
• mabrains / Analog_blocks
  Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.
  ☆29Updated 3 years ago
• muhammadaldacher / Analog-Design-of-Bootstrapped-Switch
  This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…
  ☆12Updated 6 years ago
• r09g / iadc
  12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm
  ☆22Updated 2 years ago
• Grootzz / Verilog-FIR
  FIR implemention with Verilog
  ☆50Updated 6 years ago
• iic-jku / iic-audiodac-v1
  Delta-sigma audio DAC (16b, 48kHz), intended for tape-out on MPW-5, SKY130 technology.
  ☆35Updated 3 years ago
• ADC-TEAM2020 / avsdadc_3v3
  This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…
  ☆20Updated 5 years ago
• Mshivam2409 / LDPC-Decoder
  Implementation of Partially Parellel LDPC Code Decoder in Verilog
  ☆15Updated 5 years ago
• zlijingtao / Digital-Calibration-of-SAR-ADC
  Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)
  ☆67Updated 7 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆72Updated last month
• das-dias / novaad
  An EDA tool for automatic device sizing using Gm/Id method.
  ☆14Updated last year
• Teddy-van-Jerry / ngspice-cmos
  NGSPICE Simulation of CMOS Circuits
  ☆17Updated 2 years ago
• NeuroFan / Algorithmic-SAR-ADC-simulation-files
  HSPICE and MATLAB simulation files of a tracking SAR ADC
  ☆26Updated last year
• echoPinkApple / bilinear
  Bilinear interpolation realizes image scaling based on FPGA
  ☆29Updated 5 years ago
• muhammadaldacher / Analog-Design-of-Dynamic-Comparator
  This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…
  ☆15Updated 2 years ago
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆48Updated 2 years ago
• red435 / verilog_APB_SPI_interface
  SPI interface connect to APB BUS with Verilog HDL
  ☆39Updated 4 years ago
• richard259 / serdespy
  Python library for SerDes modelling
  ☆74Updated last year
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆73Updated 3 years ago