MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/
☆10Feb 4, 2022Updated 4 years ago
Alternatives and similar repositories for Behavior-modeling-of-PLL
Users that are interested in Behavior-modeling-of-PLL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- MATLAB Implementation of a Digital PLL☆17Aug 15, 2016Updated 10 years ago
- RC Car Modelling and Trajectory Tracking Control☆28Nov 8, 2021Updated 4 years ago
- All digital PLL☆29Dec 19, 2017Updated 8 years ago
- Model SAR ADC with python!☆22Jul 8, 2022Updated 4 years ago
- CircuitPython module for the MCP4725 12-bit digital to analog converter.☆11Apr 23, 2026Updated 3 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- A MATLAB and Simulink project. Includes controller design, Simscape simulation, and sensor fusion for state estimation. By: Matteo Liguor…☆12Jun 9, 2023Updated 3 years ago
- "PLI-TDC: Super Fine Delay-Time Based Physical-Layer Identification with Time-to-Digital Converter for In-Vehicle Networks" ACM ASIACCS 2…☆14Jul 21, 2026Updated 3 weeks ago
- ☆13Aug 25, 2022Updated 3 years ago
- An attempt at MathWorks' Excellence in Innovation Project 208☆15Feb 11, 2022Updated 4 years ago
- Multi Layer Perceptron by Vivado HLS for Xilinx FPGA implementation☆12Dec 26, 2016Updated 9 years ago
- All Digital Phase-Locked Loop☆14May 22, 2023Updated 3 years ago
- Implementation of tappped delay line TDC on FPGA☆16Dec 28, 2022Updated 3 years ago
- An Equivalent Circuit model Impedance Fitting program☆11Mar 1, 2026Updated 5 months ago
- Modem Design☆21May 27, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆18Aug 31, 2020Updated 5 years ago
- Zero PDK: python-based support for open source PDKs☆28Jan 23, 2023Updated 3 years ago
- Time to Digital Converter on an FPGA☆18Oct 8, 2020Updated 5 years ago
- Single Phase Digital PLL design using TI's Delfino Launchpad☆25Feb 23, 2016Updated 10 years ago
- Implementation of SHA256 Hasher with UART Transceiver in Verilog. Designed to run on Altera's DE2 FPGA Development Board.☆16Oct 16, 2018Updated 7 years ago
- Implementation for "Generalized Zero-Shot Learning via VAE-Conditioned Generative Flow" (https://arxiv.org/abs/2009.00303)☆23Oct 4, 2020Updated 5 years ago
- ☆15Feb 24, 2019Updated 7 years ago
- FIPS 202 compliant SHA-3 core in Verilog☆24Oct 8, 2020Updated 5 years ago
- 功能简介:程序通过Technology文件转出准确的叠层和材料参数,生成XML控制文档,把GDS文件导入3D Layout或者SIwave中进行仿真,适用于2.5D/3D封装的Interposer仿真。 Readme: The program extract acc…☆32Aug 5, 2026Updated last week
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Verilog based FPGA Design of SHA256 Simulated on ModelSim☆24May 18, 2018Updated 8 years ago
- Xilinx DMA IP Drivers☆29Jul 31, 2026Updated 2 weeks ago
- A Time to Digital Converter designed for Xilinx 7-Series FPGAs☆39Jan 21, 2021Updated 5 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆39Jun 2, 2021Updated 5 years ago
- 一些经典且高质量的电子书分享☆22May 7, 2019Updated 7 years ago
- OpenGL ES 2.0 soft rendering pipeline implemented in C++.☆11Aug 15, 2019Updated 7 years ago
- A framework for FPGA emulation of mixed-signal systems☆39Jul 28, 2021Updated 5 years ago
- Project: Precise Measure of time delays in FPGA☆32Aug 3, 2017Updated 9 years ago
- Fork of github.com/UCSBarchlab/OpenTPU for the TGPTPU project☆15Jun 1, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆36May 28, 2021Updated 5 years ago
- OpenTrafficLab is a MATLAB environment capable of simulating simple traffic scenarios with modular vehicle and junction controllers.☆42Sep 23, 2025Updated 10 months ago
- Experimental/research project to build high-performance and energy-efficient virtual network functions (VNFs).☆43Jan 25, 2022Updated 4 years ago
- Implementation of the SHA256 Algorithm in Verilog☆39Jan 2, 2012Updated 14 years ago
- Elements Software Development Kit☆13Jan 8, 2026Updated 7 months ago
- Automatic generation of real number models from analog circuits☆49Apr 2, 2024Updated 2 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆12Oct 17, 2019Updated 6 years ago