Alternatives and similar repositories for synthesizable_h264:

Users that are interested in synthesizable_h264 are comparing it to the libraries listed below

• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆65Updated 5 years ago
• oprecomp / DDR4_controller
  ☆53Updated 4 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆42Updated last year
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆50Updated 5 years ago
• openasic-org / xkDLA
  xkDLA：XinKai Deep Learning Accelerator (RTL)
  ☆28Updated last year
• Xilinx / pcie-model
  PCI Express controller model
  ☆52Updated 2 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 5 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆74Updated 9 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆62Updated 3 months ago
• freecores / jpegencode
  JPEG Encoder Verilog
  ☆74Updated 2 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆31Updated 3 months ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆34Updated 3 years ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆38Updated 2 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆56Updated 4 years ago
• pulp-platform / axi_spi_slave
  ☆25Updated 3 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆25Updated 4 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆54Updated 2 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆60Updated last year
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆89Updated 5 years ago
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆35Updated 3 weeks ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆63Updated last month
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆28Updated 2 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆104Updated 3 years ago
• chipsalliance / uvm-verilator
  ☆88Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 10 months ago
• hyoukjun / OpenSMART
  Public release
  ☆50Updated 5 years ago
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆96Updated last year