Alternatives and similar repositories for synthesizable_h264

Users that are interested in synthesizable_h264 are comparing it to the libraries listed below

• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• freecores / jpegencode
  JPEG Encoder Verilog
  ☆76Updated 2 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 5 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆62Updated last year
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆124Updated last year
• oprecomp / DDR4_controller
  ☆61Updated 4 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆43Updated 2 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆77Updated 9 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆101Updated 6 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆65Updated 5 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆41Updated 4 years ago
• ultraembedded / core_jpeg
  High throughput JPEG decoder in Verilog for FPGA
  ☆233Updated 3 years ago
• LBL-CoDEx / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆171Updated 5 years ago
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆149Updated last month
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆106Updated 2 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆170Updated 7 months ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆94Updated 5 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆67Updated 6 months ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆58Updated 2 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆138Updated last year
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆59Updated 5 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆143Updated 2 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆214Updated last week
• bmartini / zynq-axis
  Hardware, Linux Driver and Library for the Zynq AXI DMA interface
  ☆101Updated 6 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 4 years ago
• tishi43 / h265_decoder
  H265 decoder write in verilog, verified on Xilinx ZYNQ7035
  ☆71Updated 3 years ago
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆107Updated this week
• pulp-platform / fpu
  ☆51Updated 6 years ago