adsc-hls / synthesizable_h264
A Synthesizable implementation of H.264 Video Decoding
☆30Updated 8 years ago
Related projects: ⓘ
- PCI Express controller model☆41Updated last year
- Basic floating-point components for RISC-V processors☆62Updated 4 years ago
- ☆44Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆51Updated 8 months ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆80Updated last year
- ☆35Updated 5 years ago
- HLS for Networks-on-Chip☆27Updated 3 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆48Updated last month
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- IEEE 754 floating point library in system-verilog and vhdl☆53Updated 3 months ago
- Examples for creating AXI-interfaced peripherals in Chisel☆70Updated 8 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆43Updated 3 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆29Updated 3 years ago
- A simple DDR3 memory controller☆49Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- Tutorials on HLS Design☆47Updated 4 years ago
- Verilog Code for a JPEG Decoder☆31Updated 6 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆52Updated last year
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆39Updated 3 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆34Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆93Updated last year
- Verilog Content Addressable Memory Module☆100Updated 2 years ago
- FGPU is a soft GPU architecture general purpose computing☆53Updated 3 years ago
- ☆22Updated 7 months ago
- Xilinx AXI VIP example of use☆29Updated 3 years ago
- BlackParrot on Zynq☆25Updated last week
- For contributions of Chisel IP to the chisel community.☆55Updated 7 months ago
- Re-coded Xilinx primitives for Verilator use☆38Updated 6 months ago
- A Fast, Low-Overhead On-chip Network☆115Updated this week