Alternatives and similar repositories for synthesizable_h264

Users that are interested in synthesizable_h264 are comparing it to the libraries listed below

• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• oprecomp / DDR4_controller
  ☆67Updated 4 years ago
• freecores / jpegencode
  JPEG Encoder Verilog
  ☆77Updated 3 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆127Updated 6 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆104Updated 7 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆114Updated 3 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated 10 months ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆52Updated 5 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆142Updated last year
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆86Updated 4 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated last year
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 6 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆95Updated 4 years ago
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆111Updated 2 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆126Updated 2 years ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆54Updated 2 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆45Updated 2 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 2 years ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆64Updated 2 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated last month
• Xilinx / pcie-model
  PCI Express controller model
  ☆68Updated 3 years ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 2 months ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆126Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆92Updated last week
• Kenji-Ishimaru / polyphony
  3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.
  ☆90Updated 5 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆80Updated 3 years ago
• ultraembedded / core_jpeg
  High throughput JPEG decoder in Verilog for FPGA
  ☆245Updated 3 years ago
• freecores / video_stream_scaler
  Video Stream Scaler
  ☆40Updated 11 years ago