adsc-hls / synthesizable_h264
A Synthesizable implementation of H.264 Video Decoding
☆32Updated 8 years ago
Alternatives and similar repositories for synthesizable_h264:
Users that are interested in synthesizable_h264 are comparing it to the libraries listed below
- Basic floating-point components for RISC-V processors☆64Updated 5 years ago
- PCI Express controller model☆48Updated 2 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- ☆53Updated 4 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆91Updated last year
- Verilog Code for a JPEG Decoder☆33Updated 6 years ago
- ☆41Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 3 years ago
- FGPU is a soft GPU architecture general purpose computing☆56Updated 4 years ago
- Tutorials on HLS Design☆51Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆58Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆59Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆34Updated 3 years ago
- Parallel Array of Simple Cores. Multicore processor.☆94Updated 5 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆37Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆64Updated 2 weeks ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆119Updated 8 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated last week
- RISCV model for Verilator/FPGA targets☆49Updated 5 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆28Updated last year
- ☆42Updated 3 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆37Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 2 months ago
- Public release☆49Updated 5 years ago
- ☆63Updated 6 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- Xilinx AXI VIP example of use☆33Updated 3 years ago