adsc-hls / synthesizable_h264Links
A Synthesizable implementation of H.264 Video Decoding
☆33Updated 9 years ago
Alternatives and similar repositories for synthesizable_h264
Users that are interested in synthesizable_h264 are comparing it to the libraries listed below
Sorting:
- PCI Express controller model☆71Updated 3 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆46Updated 2 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 11 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆105Updated 7 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- Verilog Content Addressable Memory Module☆113Updated 3 years ago
- JPEG Encoder Verilog☆78Updated 3 years ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- Video Stream Scaler☆40Updated 11 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆39Updated last year
- Ethernet switch implementation written in Verilog☆54Updated 2 years ago
- ☆69Updated 4 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 6 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- H265 decoder write in verilog, verified on Xilinx ZYNQ7035☆79Updated 4 years ago
- Tutorials on HLS Design☆52Updated 5 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆51Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆71Updated 5 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- Verilog Ethernet Switch (layer 2)☆50Updated 2 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆71Updated 6 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- ☆65Updated 3 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆127Updated last week