Alternatives and similar repositories for a0260w.github.io

Users that are interested in a0260w.github.io are comparing it to the libraries listed below

• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 7 months ago
• jiegec / verilog-format
  A naive verilog/systemverilog formatter
  ☆21Updated 3 months ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• wujun51227 / coffee-hdl
  coffeescript based hardware description language
  ☆14Updated 3 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆20Updated 3 months ago
• CircuitCoder / mill
  RV32I by cats
  ☆16Updated last year
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆37Updated 2 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• riscv-and-rust-and-decaf / riscv32i-cpu-chisel
  riscv32i-cpu
  ☆18Updated 4 years ago
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆52Updated 5 years ago
• huxuan0307 / XuanTieC910
  Rewrite XuanTieC910 with chisel3
  ☆12Updated 2 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• esa-tu-darmstadt / SCAIE-V
  An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:
  ☆16Updated last year
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆18Updated 7 months ago
• jiegec / kb
  My knowledge base
  ☆58Updated last week
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• luojia65 / DailySchedule
  ☆23Updated 3 years ago
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• ucb-bar / AuRORA
  Virtualized Accelerator Orchestration for Multi-Tenant Workloads
  ☆16Updated 7 months ago
• oscomp / proj23-lightweight-hypervisor
  在RISC-V处理器上实现一个轻量级的Hypervisor。
  ☆12Updated 4 years ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• IBM / perfect-chisel
  Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program
  ☆30Updated last month
• THU-DSP-LAB / ventus-gpgpu-isa-simulator
  Ventus GPGPU ISA Simulator Based on Spike
  ☆43Updated last week
• sarchlab / akita
  A flexible, high-performance, user-friendly computer architecture simulator engine
  ☆78Updated this week
• sequencer / arithmetic
  ☆33Updated 3 months ago
• carrv / carrv.github.io
  Workshop on Computer Architecture Research with RISC-V (CARRV)
  ☆39Updated 7 months ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆30Updated 4 years ago
• cnrv / OSEDA
  Open-Source EDA workshop for RISC-V community
  ☆12Updated 2 years ago