32位单精度浮点数加法器和除法器是用于执行符合IEEE 754标准的浮点数加法、除法运算的数字电路。这样的电路设计在现代计算机系统中扮演着重要角色，特别是在处理需要高精度计算的任务时。这个小项目实现了一个符合IEEE 754 单精度浮点数标准（32 位）的浮点数加法器与除法器的完整设计。该设计的目标是通过Verilog分别实现能够处理两输入浮点数的加法和除法运算模块。
☆15Aug 14, 2025Updated last year
Alternatives and similar repositories for 32-bit-FP-Adder-and-Divider
Users that are interested in 32-bit-FP-Adder-and-Divider are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- In this realtime car detection we are using YOLOV8 model also known as Ultralytics, for the detection of vehicles and deep_sort_pytorch. …☆17Feb 8, 2025Updated last year
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- Hardware and script files related to dynamic partial reconfiguration☆11Mar 16, 2018Updated 8 years ago
- UVM verification platform for DW_apb_i2c IP core(Master Mode)☆15Aug 21, 2023Updated 3 years ago
- 复旦数字集成电路设计自动化项目文档☆11Apr 12, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Includes the SVD-based approximation algorithms for compressing deep learning models and the FPGA accelerators exploiting such approximat…☆17Mar 3, 2023Updated 3 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆77Aug 13, 2024Updated 2 years ago
- Minimal FPGA hardware/software co-design demo with UART protocol, scratchpad memory, and an int8 dot-product accelerator, plus Python/C++…☆31May 12, 2026Updated 4 months ago
- An open silicon CHERIoT Ibex microcontroller chip☆19May 23, 2025Updated last year
- This repository contains a parameterized AXI Slave to AHB-Lite Master bridge and a UVM-based verification environment for functional, exc…☆21Mar 26, 2026Updated 6 months ago
- 国科大2023秋季学期模式识别与机器学习笔记☆36Oct 2, 2024Updated 2 years ago
- Implementation of semantic segmentation of FCN structure using KITTI road dataset😝😝😝☆34Aug 6, 2024Updated 2 years ago
- RISCV CPU implementation in SystemVerilog☆32Updated this week
- A easy general acc.☆18Mar 22, 2021Updated 5 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Builds and runs an exported impulse locally (ESP IDF)☆28Oct 30, 2025Updated 11 months ago
- 基于FP16的二维脉动阵列电路设计☆13Feb 23, 2023Updated 3 years ago
- ☆11Nov 22, 2025Updated 10 months ago
- 一个基于AXI接口的PL端卷积加速器，可由PS端调用☆12Apr 15, 2023Updated 3 years ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆36Jul 17, 2025Updated last year
- CHERI-enabled secure enclave that can be integrated as a subsytem on a system on chip.☆40Updated this week
- ICRTL Benchmark: Industrial-level RTL design challenges for evaluating PPA optimization, code generation, and LLM applications in EDA.☆35Jul 3, 2026Updated 3 months ago
- Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It …☆32Nov 21, 2020Updated 5 years ago
- Homepage built with mkdocs☆34Sep 23, 2026Updated 2 weeks ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- 哈尔滨工业大学（深圳）2021年球季学期深度学习体系结构实验☆17Oct 1, 2022Updated 4 years ago
- Design and UVM-TB of RISC -V Microprocessor☆36Jun 27, 2024Updated 2 years ago
- A comprehensive, modular learning path for mastering UVM (Universal Verification Methodology) and pyuvm (Python UVM implementation) with …☆44May 30, 2026Updated 4 months ago
- FPGA 同步FIFO与异步FIFO☆32Feb 26, 2019Updated 7 years ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆52Jul 11, 2025Updated last year
- Reimplementing the hybrid quantum-classical models from the paper "Quantum machine learning for image classification" by Arsenii Senokoso…☆33Jan 8, 2024Updated 2 years ago
- Using pytorch to implement MobileViT from Apple framework☆20Apr 24, 2023Updated 3 years ago
- Simple starter project for Hardcaml development☆37Jul 10, 2026Updated 3 months ago
- ☆20Mar 17, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆18Oct 13, 2024Updated last year
- CIS 501: Computer Architecture Fall 2019☆22Apr 21, 2020Updated 6 years ago
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆22Nov 12, 2025Updated 10 months ago
- ☆31May 15, 2020Updated 6 years ago
- ☆43Dec 21, 2025Updated 9 months ago
- Experimental Xilinx Artix-7 driven Data Center Security Communication Module☆71Dec 11, 2025Updated 9 months ago
- A batch of useful code/scripts: run commands automatically, finish repetitive stupid operations, perform format conversions, etc.☆32Mar 22, 2021Updated 5 years ago