Alternatives and similar repositories for Some-useful-Perl-Scripts

Users that are interested in Some-useful-Perl-Scripts are comparing it to the libraries listed below

• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆17Updated 10 years ago
• aignacio / ahb_lite_bus
  AHB Bus lite v3.0
  ☆16Updated 5 years ago
• muneeb-mbytes / apb_avip
  ABP Accelerated VIP
  ☆22Updated 2 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago
• 2cc2ic / DMA-S2MM-and-MM2S
  Build an open source, extremely simple DMA.
  ☆22Updated 6 years ago
• trivedidvijen / SPI-to-I2C-Protocol-Conversion-Using-Verilog
  SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.
  ☆10Updated 3 years ago
• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆14Updated last year
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆34Updated 8 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 4 years ago
• guoyijiang / VerilogModule-IIC_Master
  this repository is a project about iic master, created by gyj in second half of 2017
  ☆17Updated 7 years ago
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• pulp-platform / apb_uart_sv
  ☆13Updated 6 years ago
• lauchinyuan / Asymmetric_async_FIFO
  asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…
  ☆19Updated last year
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆44Updated last year
• AugustinJose1221 / FFTx32
  A 32 point radix-2 FFT module written in Verilog
  ☆23Updated 5 years ago
• Buddhimah / System-Bus-Design-Verilog
  This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
  ☆32Updated 5 years ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆20Updated 6 years ago
• pulp-platform / obi
  OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
  ☆14Updated this week
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• chinkwo / FPGA-multiboot
  通过SPI协议实现FPGA multiboot在线升级功能
  ☆11Updated 7 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed3
  DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8
  ☆15Updated 3 years ago
• apriya-ram / AXI_FIFO_BFM
  AXI4 with a FIFO integrated with VIP
  ☆19Updated last year
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆34Updated 8 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆42Updated 3 years ago
• Shra1-25 / Deep-Learning-implementaion-on-FPGA-using-MATLAB
  This repository contains MATLAB code which can be used to generate simulink model and HDL code for implementation on FPGA. Since HDL code…
  ☆12Updated 5 years ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆19Updated 7 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆69Updated 5 years ago
• yhqiu16 / OCOWFC
  Open-Channel Open-Way Flash Controller
  ☆17Updated 3 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆22Updated 5 months ago