Synthesizable temperature sensor for Tiny Tapeout 03, developed by IIC@JKU.
☆22Jan 1, 2024Updated 2 years ago
Alternatives and similar repositories for tt03-tempsensor
Users that are interested in tt03-tempsensor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A port of the MATLAB Delta Sigma Toolbox based on free software and very little sleep☆15Oct 20, 2022Updated 4 years ago
- OpenTwin Master☆12Updated this week
- RISC-V Playground on Nandland Go☆16Mar 2, 2023Updated 3 years ago
- Submission template for Tiny Tapeout 6 - Verilog HDL Projects☆35May 3, 2024Updated 2 years ago
- EMStudio☆20Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A set of rules and recommendations for analog and digital circuit designers.☆31Nov 4, 2024Updated 2 years ago
- IHP Open Access PDK☆18Updated this week
- IHP SG13CMOS5L PDK☆19Sep 23, 2026Updated last month
- Open-Hardware implementation of the icsprout55-pdk☆18Oct 10, 2026Updated 3 weeks ago
- ☆22Updated this week
- A Video/Camera image (over VGA) to oscilloscope X/Y mode streaming tool☆20Jan 30, 2025Updated last year
- Circuit Automatic Characterization Engine☆16Sep 24, 2026Updated last month
- Parasitic capacitance analysis of foundry metal stackups☆21Updated this week
- Simple library for EasyNixie module☆13Jan 15, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Download YouTube videos and audio with ease (support playlists). Easy to use GUI for yt-dlp written in Qt C++.☆11Feb 6, 2025Updated last year
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 3 years ago
- Open Agentic Design Automation - The open agent interface for EDA: Agent–EDA Contract☆28Aug 12, 2026Updated 2 months ago
- An Open-Source ASIC Design Template for the SG13G2 IHP Open-PDK☆21Jul 21, 2026Updated 3 months ago
- An implementation of a CPU that uses a Linear Feedback Shift Register as a Program Counter instead of a normal one☆55Apr 11, 2026Updated 6 months ago
- Fluid dynamics for Lovebyte 2022 in 512 bytes☆10Feb 12, 2022Updated 4 years ago
- Monorepo for all firmware running on our custom ECUs.☆18Updated this week
- Implementation of a RISC-V CPU in Verilog.☆21Jun 27, 2026Updated 4 months ago
- Files for Circuit Insights presentation at ISSCC 2026☆21Apr 4, 2026Updated 7 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆16Jan 14, 2021Updated 5 years ago
- JAX-based SPICE simulator with OpenVAF Verilog-A support☆32Updated this week
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆68Mar 13, 2025Updated last year
- ☆45Oct 29, 2026Updated last week
- A simple Makefile based project for WCH's CHV32V range of RISCV uControllers☆14Oct 10, 2026Updated 3 weeks ago
- mWATTBAT: The open source Radar Chip☆12Sep 1, 2025Updated last year
- Cloneless1 is an open-source tamper-resistant cryptographic ASIC design☆28Jul 30, 2026Updated 3 months ago
- Chip renders (PNG) for Tiny Tapeouts shuttles☆15Sep 23, 2026Updated last month
- Coriolis VLSI EDA Tool (LIP6)☆94Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆44Oct 6, 2022Updated 4 years ago
- COCOA: Collaborative Compendium on Analog Integrated Circuits☆32Jan 14, 2026Updated 9 months ago
- Custom Standard Cell Library for GF180MCU process node on open PDK.☆14Oct 11, 2026Updated 3 weeks ago
- Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determine…☆16Jun 15, 2016Updated 10 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆30Jan 21, 2025Updated last year
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆31Oct 13, 2026Updated 3 weeks ago
- Examples of analog circuit design with sEKV for the open source IHP 130nm technology☆33Jun 5, 2025Updated last year