Alternatives and similar repositories for logisim-RISC-V-CPU:

Users that are interested in logisim-RISC-V-CPU are comparing it to the libraries listed below

• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆62Updated 7 years ago
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆35Updated 4 years ago
• dnotq / sdram
  Simple fixed-cycle SDRAM Controller
  ☆26Updated 5 years ago
• zeeshanrafique23 / RV32I-Logisim
  RV32I single cycle simulation on open-source software Logisim.
  ☆19Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last week
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated last month
• robertdunne / FPGA-ARM
  Verilog source code for book: Computer Architecture Tutorial
  ☆25Updated 3 years ago
• PrincetonUniversity / piton-sw
  ☆18Updated 4 years ago
• robfinch / Cores
  ☆73Updated 5 months ago
• rolandbernard / kleine-riscv
  A small and simple rv32i core written in Verilog
  ☆13Updated 2 years ago
• MorrisMA / M65C02A
  Enhanced 6502/65C02 Microprogrammed FPGA Processor Core (Verilog-2001)
  ☆32Updated 3 years ago
• freecores / rtf8088
  rtf8088
  ☆10Updated 10 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆79Updated 4 years ago
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆21Updated last year
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆48Updated 3 weeks ago
• arthurbeggs / riscv-simple
  Computer architecture learning environment using FPGAs
  ☆13Updated 3 years ago
• AngeloJacobo / FPGA_SDRAM_Controller
  SDRAM controller optimized to a memory bandwidth of 316MB/s
  ☆25Updated 3 years ago
• WillGreen / timetoexplore
  Source code to accompany https://timetoexplore.net
  ☆63Updated 4 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆68Updated 2 years ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆40Updated 2 years ago
• lipro / tv80
  The TV80 (Verilog) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,tv80)
  ☆10Updated 9 years ago
• jbush001 / MiteCPU
  Minimal microprocessor
  ☆20Updated 7 years ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆44Updated last year
• rschlaikjer / fpga-3-softcores
  Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware
  ☆10Updated 4 years ago
• RobertBaruch / plugh-1
  A CPU on an FPGA that you can play Zork on
  ☆49Updated 8 years ago
• calint / tang-nano-9k--riscv--cache-psram
  RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card
  ☆28Updated last week
• tongchen126 / Boot-Debian-On-Litex-Rocket
  ☆13Updated 3 years ago
• ultraembedded / minispartan6-audio
  miniSpartan6+ (Spartan6) FPGA based MP3 Player
  ☆27Updated 5 years ago
• rdiez / jtag_dpi
  JTAG DPI module for OpenRISC simulation with Verilator
  ☆17Updated 12 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago