tibor-electronics / vga_generator
A collection of VHDL projects for generating VGA output
☆24Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for vga_generator
- A simple to use VHDL module to display text on VGA display.☆34Updated 10 years ago
- Open Processor Architecture☆26Updated 8 years ago
- Example designs for the Spartan7 "S7 Mini" FPGA board☆27Updated 5 years ago
- USB 1.1 Device IP Core☆18Updated 7 years ago
- iDEA FPGA Soft Processor☆14Updated 8 years ago
- A plain VHDL implementation of a small microprocessor fully compatible with the ISA of the well known PicoBlaze by Ken Chapman.☆21Updated 3 years ago
- Misc open FPGA flow examples☆8Updated 4 years ago
- ZPUino HDL implementation☆89Updated 6 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆34Updated 3 years ago
- OpenFPGA☆33Updated 6 years ago
- An open-source VHDL library for FPGA design.☆31Updated 2 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- understanding the tinyfpga bootloader☆24Updated 6 years ago
- Simulation VCD waveform viewer, using old Motif UI☆25Updated last year
- Basic code that displays simple shapes generated from Lattice FPGA directly to LVDS display☆27Updated 9 years ago
- Icestorm, Arachne-pnr and Yosys pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS☆38Updated 2 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆12Updated 5 years ago
- Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)☆20Updated 8 years ago
- Video Effects on VGA☆14Updated 5 years ago
- CRUVI Standard Specifications☆17Updated 6 months ago
- Simple USB to PWM Peripheral using Lattice iCEStick (Hackaday demo)☆22Updated 4 years ago
- CMake template for Verilog and VHDL project and Altera/Xilinx FPGA target☆20Updated last year
- Small footprint and configurable Inter-Chip communication cores☆54Updated last month
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- Yosys Plugins☆20Updated 5 years ago