☆15Aug 6, 2018Updated 7 years ago
Alternatives and similar repositories for resq
Users that are interested in resq are comparing it to the libraries listed below
Sorting:
- This is a repo for hosting the projects in SIGCOMM 2019 Hackathon☆10Jul 14, 2019Updated 6 years ago
- X-Change: Efficient Metadata Management Model for Packet Processing☆18Jan 19, 2021Updated 5 years ago
- ☆20May 26, 2021Updated 4 years ago
- ☆10May 30, 2017Updated 8 years ago
- P4 compatible HLS modules☆11Apr 23, 2018Updated 7 years ago
- ☆31Jul 18, 2019Updated 6 years ago
- ☆15Feb 15, 2018Updated 8 years ago
- A superoptimizing compiler for packet-processing☆30Jun 16, 2023Updated 2 years ago
- Enhanced PQOS (Intel RDT Software) with DDIO-related Functionalities☆16May 25, 2022Updated 3 years ago
- The Programmable Data Plane: Reading List☆52Sep 29, 2020Updated 5 years ago
- ☆12Oct 16, 2021Updated 4 years ago
- The Domino compiler to run packet programs on pipelined switches☆29Aug 12, 2021Updated 4 years ago
- Morpheus: Domain Specific Run Time Optimization for Software Data Planes -- Presented at ASPLOS22☆35Apr 11, 2024Updated last year
- ☆18Jun 29, 2018Updated 7 years ago
- p4 language running on Snabb Switch (work-in-progress)☆12Feb 27, 2016Updated 10 years ago
- Relevant Material for SIGCOMM 2020 paper "Contention-Aware Performance Prediction for Virtualized Network Functions"☆17Jul 1, 2020Updated 5 years ago
- ☆11Jan 29, 2015Updated 11 years ago
- The code runs on the netronome smart card to filtering PPPoE and PPP control plane packet send to vbras and Decap\Encap data plane packet…☆11Jun 21, 2017Updated 8 years ago
- ☆17Oct 17, 2025Updated 5 months ago
- P4 Implementation of Service Function Chaining in IEEE ICCE-Asia'20☆12May 6, 2024Updated last year
- Latex Template for CoNEXT 2018☆19Apr 11, 2022Updated 3 years ago
- Slice-aware Memory Management - Exploiting NUCA Characteristic of LLC in Intel Processors☆41May 20, 2019Updated 6 years ago
- ☆52Oct 4, 2025Updated 5 months ago
- Extend Open vSwitch with BPF programs at runtime☆35Jan 29, 2020Updated 6 years ago
- EasyNIC: an easy-to-use host interface for network cards☆43May 30, 2018Updated 7 years ago
- PacketMill: Toward per-core 100-Gbps Networking☆63Feb 1, 2022Updated 4 years ago
- https://rs3lab.github.io/SynCord/☆26Nov 23, 2022Updated 3 years ago
- ☆10Nov 22, 2020Updated 5 years ago
- ☆24Oct 27, 2025Updated 4 months ago
- ☆60Oct 29, 2020Updated 5 years ago
- NeuroCuts is a deep RL algorithm for generating optimized packet classification trees.☆75Jun 4, 2020Updated 5 years ago
- ☆29Nov 15, 2022Updated 3 years ago
- A Throughput-Centric View of the Performance of Datacenter Topologies [SIGCOMM'21]☆10May 25, 2021Updated 4 years ago
- ☆16Oct 26, 2020Updated 5 years ago
- A benchmarking methodology to evaluate the performance of state-of-the-art software virtual switches☆23Jul 11, 2022Updated 3 years ago
- High-Speed Stateful Packet Processor for Programmable Switches☆14Dec 18, 2022Updated 3 years ago
- HyperV: High-Performance Virtualization of the Programmable Data Plane☆12Oct 22, 2017Updated 8 years ago
- ☆27Apr 20, 2021Updated 4 years ago
- The code for both the framework and experiments from the NSDI '19 paper "Loom: Flexible and Efficient NIC Packet Scheduling"☆31Feb 4, 2019Updated 7 years ago