This repo contains the Assignments from Cornell Tech's ECE 5545 - Machine Learning Hardware and Systems offered in Spring 2023
☆45May 31, 2023Updated 2 years ago
Alternatives and similar repositories for ECE5545-ML-Hardware-Systems
Users that are interested in ECE5545-ML-Hardware-Systems are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆16Sep 27, 2022Updated 3 years ago
- ☆12Sep 18, 2024Updated last year
- ☆11Jun 11, 2021Updated 4 years ago
- ☆27Feb 27, 2025Updated last year
- 东秦第五届龙芯班仓库☆11Oct 22, 2023Updated 2 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆26Dec 18, 2024Updated last year
- This repo contains the skeleton scripts for running a full RTL2GDS flow using Cadence tools, as demonstrated in the Full RTL2GDS Demo pre…☆72Oct 18, 2025Updated 6 months ago
- ☆69Apr 22, 2025Updated 11 months ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 5 months ago
- Lab 5 project of MIT-6.5940, deploying LLaMA2-7B-chat on one's laptop with TinyChatEngine.☆18Dec 1, 2023Updated 2 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆60Nov 22, 2023Updated 2 years ago
- A Portable Linux-based Firmware for NVMe Computational Storage Devices☆31Jun 10, 2025Updated 10 months ago
- QuardStar Tutorial is all you need !☆16Sep 11, 2024Updated last year
- Simple UVM environment for experimenting with Verilator.☆38Mar 23, 2026Updated 3 weeks ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- DEsign 16-bit ALU using Verilog☆10Feb 13, 2016Updated 10 years ago
- DGEMM on KNL, achieve 75% MKL☆19May 19, 2022Updated 3 years ago
- Innervator: Hardware Acceleration for Neural Networks☆19Aug 3, 2024Updated last year
- ☆29Apr 7, 2025Updated last year
- ☆36Apr 9, 2026Updated last week
- ASIC Design of the openSPARC Floating Point Unit☆15Mar 13, 2017Updated 9 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 3 years ago
- A repository for exploring LLM-assisted code conversion to TL-Verilog.☆15Feb 20, 2026Updated last month
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆14Aug 25, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware☆13Aug 24, 2020Updated 5 years ago
- The Linux Foundation/Redwood EDA "Building a RISC-V CPU" Course content, also available via EdX.☆18Jul 9, 2024Updated last year
- ☆21Apr 9, 2025Updated last year
- This is a passion project where I aim to explore the RTL design topics of my interest.☆13May 23, 2025Updated 10 months ago
- ☆10Nov 5, 2019Updated 6 years ago
- git presentaion for APT subject CMP26 - 2024☆13Apr 25, 2024Updated last year
- ☆66Feb 11, 2026Updated 2 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆197Jan 8, 2026Updated 3 months ago
- UC Berkeley CS152 Computer Architecture and Engineering Labs☆26Jun 17, 2020Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆138Jul 22, 2025Updated 8 months ago
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆14Jan 2, 2021Updated 5 years ago
- ☆15May 8, 2025Updated 11 months ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆27Nov 1, 2025Updated 5 months ago
- ETH Computer Architecture - Fall 2020☆13Feb 26, 2021Updated 5 years ago
- ☆13Mar 5, 2024Updated 2 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆36Mar 14, 2021Updated 5 years ago