Alternatives and similar repositories for bare-metal-cstdlib

Users that are interested in bare-metal-cstdlib are comparing it to the libraries listed below

• lupyuen / tcc-riscv32-wasm
  TCC (Tiny C Compiler) for 64-bit RISC-V, compiled to WebAssembly with Zig Compiler
  ☆53Updated last year
• machdyne / kakao
  Kakao Linux
  ☆39Updated 7 months ago
• jevinskie / riscv-smol-linux-kernel
  Patched sources/configs for RISC-V Linux with musl-based toolchain targeting 8 MB RAM
  ☆24Updated 3 years ago
• Mr-Bossman / KISC-V
  KISCV, a KISS principle riscv32i CPU
  ☆26Updated last year
• chuckb / riscv-helloworld-c
  A bare metal hello world in C for Risc-V using QEMU to test
  ☆14Updated last year
• popovicu / linux-no-mmu-userspace-example
  ☆45Updated 2 years ago
• sellicott / tcc-riscv32
  Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…
  ☆73Updated last week
• hamsternz / emulate-risc-v
  A very simple RISC-V ISA emulator.
  ☆39Updated 5 years ago
• YoWASP / vscode
  YoWASP toolchain for Visual Studio Code
  ☆24Updated last month
• suarezvictor / litex_imgui_usb_demo
  Soft USB for LiteX
  ☆50Updated 3 months ago
• grayresearch / xsoc-xr16
  Snapshot of the April 2000 XSOC/xr16 Project Beta 0.93, collateral for Jan Gray's series "Building a RISC System in an FPGA" published in…
  ☆12Updated 3 years ago
• Wren6991 / NorForkConditionally
  What's the simplest CPU you can build?
  ☆36Updated 11 years ago
• olofk / qerv
  ☆19Updated 8 months ago
• projf / isle
  Isle FPGA Computer
  ☆60Updated last week
• TinyTapeout / vga-playground
  Playground for VGA projects on Tiny Tapeout
  ☆70Updated last month
• aniketnk / circular-queue-verilog
  Implementation of a circular queue in hardware using verilog.
  ☆17Updated 6 years ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆60Updated 5 years ago
• fwsGonzo / bigassm
  Assemble 128-bit RISC-V
  ☆46Updated 2 years ago
• mballance / fwrisc-s
  ☆10Updated 6 years ago
• howerj / lfsr-vhdl
  An implementation of a CPU that uses a Linear Feedback Shift Register as a Program Counter instead of a normal one
  ☆54Updated 7 months ago
• mirimmad / riscv
  RISC-V(RV32IM) emulator with support for syscalls.
  ☆30Updated 2 years ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆87Updated 6 years ago
• whitequark / bfcpu2
  A pipelined brainfuck softcore in Verilog
  ☆19Updated 11 years ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated last week
• lupyuen / nuttx-tinyemu
  Apache NuttX RTOS in the Web Browser: TinyEMU with VirtIO
  ☆23Updated last year
• BrunoLevy / TinyPrograms
  Tiny programs from various sources, for testing softcores
  ☆137Updated 4 months ago
• mausimus / rvcc
  Standalone C compiler for RISC-V and ARM
  ☆97Updated last year
• FPGAwars / FLIX-V
  FLIX-V: FPGA, Linux and RISC-V
  ☆41Updated 2 years ago
• pineapple-one / logisim-simulation
  Simulation in Logisim-Evolution HC
  ☆34Updated 4 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆59Updated 8 months ago