Open source FPGA silicon
β349Sep 5, 2026Updated last month
Alternatives and similar repositories for aegis
Users that are interested in aegis are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Modular RISC-V implementation & SoCβ23Oct 9, 2026Updated last week
- An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain ποΈβ308Updated this week
- A tiny FABulous FPGA for TTIHP26aβ15Apr 9, 2026Updated 6 months ago
- Fabric generator and CAD tools graphical frontendβ19Oct 6, 2026Updated last week
- Open-source RTL logic simulator with GPU acceleration (Metal, CUDA, HIP/AMD)β88Aug 10, 2026Updated 2 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer β’ AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Exploring gate level simulationβ60Mar 27, 2026Updated 6 months ago
- Greyhound on IHP SG13G2 0.13 ΞΌm BiCMOS processβ111Aug 31, 2026Updated last month
- ROHD Wave Viewer is a waveform viewer Flutter app, part of the ROHD ecosystem. It works in-browser, integrated as a Flutter widget, used β¦β14Oct 8, 2026Updated last week
- β175Jan 4, 2026Updated 9 months ago
- FPGA synthesis toolβ146Sep 24, 2026Updated 3 weeks ago
- IHP 130nm ASIC tapeout of a 2x2 bfloat16 matrix matrix multiplication with DFT infrastructure. Iteration on the previous accelerator tapeβ¦β44Jul 10, 2026Updated 3 months ago
- Netlist API (and more) for EDA flow developmentβ165Updated this week
- Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Boardβ25Nov 17, 2021Updated 4 years ago
- Tiny Tapeout project build tools + chip integration scriptsβ36Sep 21, 2026Updated 3 weeks ago
- 1-Click AI Models by DigitalOcean Gradient β’ AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.β48Jul 13, 2026Updated 3 months ago
- Zucker SOCβ17Jun 11, 2025Updated last year
- Elements Software Development Kitβ13Jan 8, 2026Updated 9 months ago
- ASIC implementation flow infrastructure, successor to OpenLaneβ587Updated this week
- A hardware component library developed with ROHD.β117Updated this week
- Full Speed USB DFU interface for FPGA and ASIC designsβ21Mar 10, 2024Updated 2 years ago
- open source hardware synthesis. SystemVerilog, VHDL and ABEL-HDL to gate-level netlistsβ45Aug 25, 2026Updated last month
- A novel Design-for-Test flow using LibreLaneβ50May 9, 2026Updated 5 months ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppoβ¦β647Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer β’ AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Open-source PDK version managerβ68Updated this week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.β290Updated this week
- β22Sep 23, 2026Updated 3 weeks ago
- Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotbβ61Sep 19, 2026Updated 3 weeks ago
- C compiler in Zigβ22Jul 20, 2025Updated last year
- A minimalist HDL built entirely from logic gates for education and experimentation. Compiles circuits to C so that they can run anywhereβ51Sep 23, 2026Updated 3 weeks ago
- HeiChips 2025 LibreLane Workshopβ18Aug 25, 2025Updated last year
- Project template for wafer.space MPW runs using the gf180mcu PDKβ58Oct 9, 2026Updated last week
- Baochip 1x Siliconβ484Sep 13, 2026Updated last month
- End-to-end encrypted cloud storage - Proton Drive β’ AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Repository containing ULX3S blink LED binariesβ16May 16, 2022Updated 4 years ago
- Library of FPGA architecturesβ33Sep 28, 2026Updated 2 weeks ago
- [Moved to Codeberg] Another size-optimized RISC-V CPU for your consideration.β61May 10, 2026Updated 5 months ago
- Debug waveforms with GDBβ33Nov 12, 2025Updated 11 months ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.β146Updated this week
- Digital logic benchmark suiteβ89Sep 28, 2026Updated 2 weeks ago
- HDL-first mixed-signal co-simulation: embed ngspice circuits in Verilog through VPIβ75Sep 22, 2026Updated 3 weeks ago