IBM / microprobeLinks
Microprobe: Microbenchmark generation framework
☆22Updated 3 weeks ago
Alternatives and similar repositories for microprobe
Users that are interested in microprobe are comparing it to the libraries listed below
Sorting:
- RiscyOO: RISC-V Out-of-Order Processor☆163Updated 5 years ago
- An open-source custom cache generator.☆34Updated last year
- Chisel RISC-V Vector 1.0 Implementation☆113Updated last week
- Consistency checker for memory subsystem traces☆23Updated 9 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 5 months ago
- Hardware generator debugger☆76Updated last year
- ☆89Updated last month
- RISC-V RV64GC emulator designed for RTL co-simulation☆232Updated 10 months ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆159Updated 3 years ago
- The specification for the FIRRTL language☆60Updated last week
- OmniXtend cache coherence protocol☆82Updated 4 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- ☆50Updated 2 weeks ago
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆41Updated 11 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆147Updated last month
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated 2 years ago
- high-performance RTL simulator☆178Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- ☆108Updated last month
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆103Updated 2 weeks ago
- Extremely Simple Microbenchmarks☆36Updated 7 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 weeks ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆180Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- Lipsi: Probably the Smallest Processor in the World☆87Updated last year
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- RISC-V Formal Verification Framework☆153Updated this week
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- The multi-core cluster of a PULP system.☆108Updated last week