IBM / microprobeLinks
Microprobe: Microbenchmark generation framework
☆23Updated 3 months ago
Alternatives and similar repositories for microprobe
Users that are interested in microprobe are comparing it to the libraries listed below
Sorting:
- Consistency checker for memory subsystem traces☆23Updated 9 years ago
- ☆51Updated 3 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- An open-source custom cache generator.☆34Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆180Updated 7 months ago
- OmniXtend cache coherence protocol☆82Updated 6 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆168Updated 5 years ago
- Chisel RISC-V Vector 1.0 Implementation☆124Updated 2 months ago
- ☆89Updated 3 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆87Updated 2 months ago
- Hardware generator debugger☆77Updated last year
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆162Updated 3 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆130Updated last week
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆151Updated last month
- Connectal is a framework for software-driven hardware development.☆176Updated 2 years ago
- The specification for the FIRRTL language☆62Updated 2 weeks ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆107Updated 3 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- CVA6 SDK containing RISC-V tools and Buildroot☆76Updated 3 weeks ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆51Updated 4 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 4 years ago
- The Task Parallel System Composer (TaPaSCo)☆114Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆78Updated last year
- For contributions of Chisel IP to the chisel community.☆69Updated last year