Alternatives and similar repositories for lamina

Users that are interested in lamina are comparing it to the libraries listed below

• dougallj / asil
  ☆33Updated last year
• herumi / xbyak_riscv
  ☆48Updated this week
• travisdowns / robsize
  ROB size testing utility
  ☆156Updated 3 years ago
• weirdindiankid / cacheflow
  CacheFlow is a Linux kernel module that exposes the contents of the last-level cache on *most* ARM machines.
  ☆17Updated last year
• jdmccalpin / Intel_Address_Hash
  Use hardware performance counters to find mapping of addresses to L3 slices in Intel processors
  ☆16Updated 2 years ago
• ocxtal / insn_bench_aarch64
  Instruction latency & throughput profiler for AArch64
  ☆37Updated last month
• shacron / sled
  Sled System Emulator
  ☆28Updated 3 months ago
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 5 years ago
• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆99Updated 3 years ago
• nbdd0121 / r2vm
  Rust RISC-V Virtual Machine
  ☆106Updated 9 months ago
• riscv / riscv-cfi
  This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …
  ☆91Updated 2 weeks ago
• revyos / xuantie-c900-bugs
  Summary of bugs in Xuantie C9XX core design. include C906/C908/C910/C920
  ☆21Updated last month
• preames / public-notes
  A collection of (public) notes on assorted topics
  ☆79Updated 3 weeks ago
• PSPReverse / amd-nv-tool
  amd-nv-tool can extract and modify information from BIOS images of AMD systems
  ☆14Updated 2 years ago
• lethalbit / discretize
  A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad
  ☆12Updated last year
• asmjit / cult
  CPU Ultimate Latency Test.
  ☆110Updated last month
• dzaima / intrinsics-viewer
  x86-64, ARM, and RVV intrinsics viewer
  ☆55Updated 3 months ago
• pydrofoil / pydrofoil
  A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
  ☆76Updated this week
• blitz / kernel_entry_benchmark
  Microbenchmarks for x86_64 kernel entry methods
  ☆19Updated 3 years ago
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆77Updated 2 weeks ago
• franzflasch / leiwand_rv32
  RISC-V RV32I CPU written in verilog
  ☆10Updated 5 years ago
• cwabbott0 / mali-isa-docs
  A collection of reverse-engineered documentation for the instruction sets for various generations of Mali GPU's.
  ☆37Updated 7 years ago
• lcq2 / risc-666
  RISC-V user-mode emulator that runs DooM
  ☆54Updated 6 years ago
• fintelia / riscv-decode
  Simple library for decoding RISC-V instructions
  ☆24Updated 11 months ago
• VANDAL / prism
  Modular, flexible, cross-platform workload profiling and characterization
  ☆13Updated 4 years ago
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 3 years ago
• riscv-non-isa / riscv-security-model
  RISC-V Security Model
  ☆30Updated 2 weeks ago
• stephand / ptlsim
  Stable, non-KVM version of PTLsim.
  ☆29Updated 9 years ago
• joeywang4 / Transient-Weird-Machine
  Microarchitectural weird machine implementation using exceptions, TSX, branch predictors, and branch target buffers.
  ☆14Updated 2 years ago
• ashwio / arm64-sysreg-lib
  Header-only C library for reading/writing 64-bit Arm registers, automatically generated by parsing the AArch64 System Register XML.
  ☆30Updated 4 years ago