idanw / Verilog-Pac-ManLinks
Verilog implementation of Pac-Man made for a class's final project
☆19Updated 13 years ago
Alternatives and similar repositories for Verilog-Pac-Man
Users that are interested in Verilog-Pac-Man are comparing it to the libraries listed below
Sorting:
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆33Updated 9 months ago
- Wishbone interconnect utilities☆43Updated 10 months ago
- Minimal DVI / HDMI Framebuffer☆82Updated 5 years ago
- Small (Q)SPI flash memory programmer in Verilog☆66Updated 3 years ago
- Master-thesis-final☆19Updated 2 years ago
- An CAN bus Controller implemented in Verilog☆50Updated 10 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆47Updated last year
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 5 years ago
- SDRAM controller with multiple wishbone slave ports☆29Updated 7 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆92Updated 3 years ago
- TCP/IP controlled VPI JTAG Interface.☆69Updated 11 months ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆32Updated 2 years ago
- I2C Master Verilog module☆34Updated 6 months ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- Conecting the Litefury FPGA accelerator to Raspberry Pi 5 over PCIe gen2 x1☆37Updated last year
- Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board☆19Updated 4 years ago
- Wishbone to AXI bridge (VHDL)☆44Updated 6 years ago
- Verilog wishbone components☆124Updated last year
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆92Updated 7 years ago
- Digital FM Radio Receiver for FPGA☆63Updated 9 years ago
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆25Updated 5 years ago
- Wishbone controlled I2C controllers☆55Updated last year
- Project and presentation for SpaceX Application☆14Updated 8 years ago
- This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from C…☆19Updated 4 months ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆36Updated last year
- A version of f32c/arduino that works with the SpinalHDL Vexriscv Murax SoC☆14Updated 6 years ago
- SDRAM controller for MIPSfpga+ system☆24Updated 5 years ago
- Projects using the Sipeed Tang Primer FPGA development board☆15Updated 5 years ago