yet another model checker
☆21Feb 27, 2026Updated this week
Alternatives and similar repositories for rumur
Users that are interested in rumur are comparing it to the libraries listed below
Sorting:
- We solve the two challenges architects face when designing heterogeneous processors with cache coherent shared memory. First, we develop …☆20Jan 7, 2022Updated 4 years ago
- RISC-V Formal in Chisel☆12Apr 9, 2024Updated last year
- The Cubicle model checker☆14Jan 12, 2026Updated last month
- Cross platform Instant Outbidding Bot, Instant Outbidder Bot is designed to outbid all real-time bids within a second by percentage incre…☆100Jan 17, 2023Updated 3 years ago
- Memory consistency model checking and test generation library.☆16Oct 14, 2016Updated 9 years ago
- Byzantine model checker☆21Mar 7, 2023Updated 2 years ago
- Boolean Expressions☆21Nov 5, 2018Updated 7 years ago
- CN separation logic refinement type system for C☆46Feb 16, 2026Updated 2 weeks ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆102Updated this week
- xDEVS: A cross-platform Discrete EVent System simulator☆14Nov 14, 2025Updated 3 months ago
- A linearizability checker for concurrent data structures☆12Aug 3, 2023Updated 2 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- Sequence Planner☆12Nov 17, 2017Updated 8 years ago
- Translate a subset of C to Verilog☆11May 8, 2019Updated 6 years ago
- A Terraria clone in Python, just for fun☆10Jun 7, 2020Updated 5 years ago
- The Unified TileLink Memory Subsystem Tester for XiangShan☆12Jan 7, 2026Updated last month
- Controlled Invariant Sets in Two Moves☆14Dec 21, 2021Updated 4 years ago
- A copy of the latest version of MVSIS☆12Apr 18, 2021Updated 4 years ago
- Solver for Constrained Horn Clauses☆50Updated this week
- A RISC-V RV32 model ready for SMT program synthesis.☆12Jun 23, 2021Updated 4 years ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14May 7, 2022Updated 3 years ago
- Proof combinators used in Liquid Haskell for theorem proving☆12Mar 28, 2018Updated 7 years ago
- A PyTorch implementation of the paper https://arxiv.org/abs/1709.04875☆10Jul 22, 2020Updated 5 years ago
- Netlist and Verilog Haskell Package☆19Nov 21, 2010Updated 15 years ago
- Modular, flexible, cross-platform workload profiling and characterization☆13Mar 1, 2021Updated 5 years ago
- Nucleic acid sequence designer☆12Jan 29, 2026Updated last month
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- BuDDy BDD package (with CMake support)☆15May 7, 2024Updated last year
- Iodine: Verifying Constant-Time Execution of Hardware☆15Mar 29, 2021Updated 4 years ago
- Official Website of Hypercrx☆13Jan 8, 2025Updated last year
- Repository of benchmarks for SYNTCOMP☆14Sep 16, 2025Updated 5 months ago
- stateless model checking for thread libraries, kernels, and transactional memory☆10Dec 26, 2018Updated 7 years ago
- The PRISM benchmark suite: A set of probabilistic models and accompanying probabilistic model checking tasks for testing and benchmarking…☆11Mar 12, 2025Updated 11 months ago
- Tools for quantum circuits synthesis, optimization and others.☆21Nov 18, 2025Updated 3 months ago
- OxiZ is a high-performance Satisfiability Modulo Theories (SMT) solver written entirely in Rust. This project is part of an initiative to…☆38Feb 6, 2026Updated 3 weeks ago
- work in progress, playing around with btor2 in rust☆12Updated this week
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 3 years ago
- Common lisp bindings to CUDD.☆13Jan 3, 2018Updated 8 years ago
- An Emacs major mode to edit and run SMTLIB v2 files☆10Nov 14, 2015Updated 10 years ago