Alternatives and similar repositories for Awesome-RISC-V

Users that are interested in Awesome-RISC-V are comparing it to the libraries listed below

• lmxyy / Computer-Architecture-Task-2
  Riscv32 CPU Project
  ☆93Updated 7 years ago
• VenciFreeman / RISC-V
  A simple RISC-V CPU written in Verilog.
  ☆66Updated last year
• OSCPU / NutShell-doc
  ☆123Updated 3 years ago
• hehao98 / RISCV-Simulator
  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation
  ☆192Updated last year
• LiHao217 / RISC-V_article_paper_src
  riscv资料、论文等
  ☆143Updated 6 years ago
• riscv-mcu / hbird-sdk
  OpenSource HummingBird RISC-V Software Development Kit
  ☆163Updated last year
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆110Updated 3 years ago
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆423Updated last week
• meton-robean / ResearchNote
  通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …
  ☆77Updated 5 years ago
• DawnCarol / DawnCarol
  ☆206Updated 5 months ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆66Updated last week
• runninglinuxkernel / riscv_programming_practice
  ☆218Updated 2 years ago
• cnrv / home
  为推广RISC-V尽些薄力
  ☆313Updated 2 years ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆304Updated 7 years ago
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆160Updated 8 months ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆75Updated this week
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆320Updated 9 months ago
• Lingrui98 / RISC-V-book
  A translation project of the RISC-V reader
  ☆175Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆52Updated 3 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆180Updated 11 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆153Updated last week
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• cnrv / riscv-soc-book
  关于RISC-V你所需要知道的一切
  ☆561Updated 2 years ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆42Updated 7 years ago
• accomdemy / accomdemy_rv32i
  伴伴學 RISC-V RV32I Architecture CPU
  ☆30Updated 2 years ago
• plctlab / writing-your-first-riscv-simulator
  《从零开始的RISC-V模拟器开发》配套的PPT和教学资料
  ☆223Updated 4 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆137Updated 2 years ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆163Updated 3 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 5 years ago