Alternatives and similar repositories for Awesome-RISC-V

Users that are interested in Awesome-RISC-V are comparing it to the libraries listed below

• OSCPU / NutShell-doc
  ☆124Updated 3 years ago
• VenciFreeman / RISC-V
  A simple RISC-V CPU written in Verilog.
  ☆68Updated last year
• runninglinuxkernel / riscv_programming_practice
  ☆224Updated 2 years ago
• accomdemy / accomdemy_rv32i
  伴伴學 RISC-V RV32I Architecture CPU
  ☆31Updated 3 years ago
• LiHao217 / RISC-V_article_paper_src
  riscv资料、论文等
  ☆144Updated 7 years ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆68Updated 2 weeks ago
• lmxyy / Computer-Architecture-Task-2
  Riscv32 CPU Project
  ☆94Updated 7 years ago
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆334Updated last month
• hehao98 / RISCV-Simulator
  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation
  ☆200Updated last year
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆176Updated 3 years ago
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆427Updated this week
• cnrv / home
  为推广RISC-V尽些薄力
  ☆312Updated 2 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆138Updated 3 years ago
• Lingrui98 / RISC-V-book
  A translation project of the RISC-V reader
  ☆174Updated last year
• TYOD-SOC / RISCV-Accelerator
  ☆37Updated 7 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆134Updated 2 years ago
• meton-robean / ResearchNote
  通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …
  ☆78Updated 5 years ago
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆180Updated 4 years ago
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆156Updated 6 years ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆326Updated 7 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆217Updated last month
• DawnCarol / DawnCarol
  ☆210Updated 8 months ago
• mathis-s / SoomRV
  A simple superscalar out-of-order RISC-V microprocessor
  ☆230Updated 9 months ago
• learnwithexamples / learnsystemc
  Learn systemC with examples
  ☆125Updated 3 years ago
• AleksandarKostovic / SystemC-tutorial
  Brief SystemC getting started tutorial
  ☆95Updated 6 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆221Updated 5 years ago
• cnrv / RVSC2023
  RISC-V Summit China 2023
  ☆40Updated 2 years ago
• OpenXiangShan / NEMU
  Super fast RISC-V ISA emulator for XiangShan processor
  ☆302Updated this week
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆76Updated last month