CNLHC / Awesome-RISC-V
☆29Updated 6 years ago
Alternatives and similar repositories for Awesome-RISC-V:
Users that are interested in Awesome-RISC-V are comparing it to the libraries listed below
- ☆122Updated 2 years ago
- A simple RISC-V CPU written in Verilog.☆62Updated 7 months ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆91Updated last month
- AZPR cpu.《CPU自制入门》附录的Verilog代码,其中的日文注释翻译成了中文。☆39Updated 4 years ago
- Wrapper for Rocket-Chip on FPGAs☆130Updated 2 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆57Updated 3 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆38Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆150Updated 5 months ago
- ☆36Updated 6 years ago
- riscv资料、论文等☆143Updated 6 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆132Updated 9 months ago
- 通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …☆75Updated 4 years ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆52Updated 4 years ago
- Collect some IC textbooks for learning.☆128Updated 2 years ago
- RISC-V SystemC-TLM simulator☆300Updated 3 months ago
- ☆85Updated 2 years ago
- ☆118Updated 5 years ago
- RISC-V Summit China 2023☆42Updated last year
- ☆171Updated last week
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆39Updated 7 years ago
- OpenSource HummingBird RISC-V Software Development Kit☆153Updated last year
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆59Updated last year
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆103Updated 2 years ago
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆234Updated 3 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆49Updated 2 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 8 months ago
- ☆82Updated last month
- Riscv32 CPU Project☆86Updated 7 years ago
- Documentation for RISC-V Spike☆100Updated 6 years ago