Alternatives and similar repositories for IC-Contest

Users that are interested in IC-Contest are comparing it to the libraries listed below

• Ni-ChiTing / IC_contest_cell_based_design
  ☆14Updated 4 years ago
• derek8955 / ic_contest
  IC Contest
  ☆42Updated 2 years ago
• Baechu44 / ic_contest
  ☆10Updated last year
• NCTUTHEBEST / ICLAB_2023_FALL
  紀錄一下自己寫過的所有Lab
  ☆38Updated last year
• krz-max / Digital-Circuits-and-Systems
  [NYCU 2021 Spring] Digital Circuits and Systems
  ☆21Updated last year
• suchuankai / IC-contest
  IC-contest 2012~2024
  ☆21Updated last year
• kerryliukk / NTHU-ICLAB
  清華大學 | 積體電路設計實驗 (IC LAB) | 110上
  ☆46Updated 3 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆236Updated 2 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆177Updated 6 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆122Updated 4 months ago
• HsuChiChen / nycu-iclab-2023-fall
  交通大學iclab 2023 fall
  ☆44Updated last year
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆123Updated 5 years ago
• Buck008 / Transformer-Accelerator-Based-on-FPGA
  You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…
  ☆218Updated last year
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆314Updated last year
• Ziheng-W / systolic-array-verilog
  verilog实现systolic array及配套IO
  ☆10Updated last year
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆142Updated 6 years ago
• boaaaang / CNN-Implementation-in-Verilog
  Convolutional Neural Network RTL-level Design
  ☆72Updated 4 years ago
• taoyilee / clacc
  Deep Learning Accelerator (Convolution Neural Networks)
  ☆196Updated 8 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆143Updated 7 months ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆39Updated 3 years ago
• GuoningHuang / FPGA-CNN-accelerator-based-on-systolic-array
  2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
  ☆212Updated 2 months ago
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆41Updated 2 years ago
• FedericoSerafini / HLS-CNN
  High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
  ☆41Updated last year
• dldldlfma / super_small_toy_tpu
  ☆45Updated 4 years ago
• XDEv11 / ICLAB-2022-FALL
  ☆43Updated 2 years ago
• bol-edu / 2022-fall-ntu
  ☆33Updated last year
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆173Updated last year
• laplaceyc / VLSI_Design-Implementation
  This repo is "NTHU VLSI System Design and Implementation" course project.
  ☆13Updated 8 years ago
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆22Updated last year
• bol-edu / HLS-SOC-Discussions
  Discussion Forum for High-Level Synthesis (HLS) Courses in Taiwan.
  ☆56Updated 2 years ago