[NYCU 2021 Spring] Digital Circuits and Systems
☆26Jan 26, 2024Updated 2 years ago
Alternatives and similar repositories for Digital-Circuits-and-Systems
Users that are interested in Digital-Circuits-and-Systems are comparing it to the libraries listed below
Sorting:
- 108下 計算機組織 Computer Organization 李毅郎☆10Feb 22, 2021Updated 5 years ago
- 超詳細 ICLAB 2024 Spring 修課心得 & 修課指南，含資源整理☆120Apr 9, 2025Updated 10 months ago
- ☆26Sep 30, 2025Updated 5 months ago
- 交通大學iclab 2023 fall☆44Oct 18, 2024Updated last year
- ☆20Apr 2, 2023Updated 2 years ago
- IC Contest☆44Mar 28, 2023Updated 2 years ago
- 紀錄一下自己寫過的所有Lab☆37Jan 18, 2024Updated 2 years ago
- Memory Compiler Tutorial☆14Aug 2, 2022Updated 3 years ago
- ☆14Feb 13, 2022Updated 4 years ago
- NYCU ICLAB 2025 spring codes & 心得☆21Jan 1, 2026Updated 2 months ago
- NCTU 2021 Spring Integrated Circuit Design Laboratory☆198Apr 2, 2023Updated 2 years ago
- Deep Learning & VLSI Crash Course for New Members☆40Aug 6, 2025Updated 7 months ago
- ☆14May 30, 2021Updated 4 years ago
- IC-contest 2012~2024☆22Apr 30, 2024Updated last year
- ☆22Jan 9, 2024Updated 2 years ago
- ☆33Jan 6, 2026Updated 2 months ago
- Hybrid Precoding/Combining for Rich or Poor Scattering Environments☆11Jul 19, 2019Updated 6 years ago
- 🤖 An automated NTU Thesis LaTeX continuous integration and continuous deploying service built up with GitHub Actions.☆10May 8, 2020Updated 5 years ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- RTL implementation of TFlite FPGA accelerator and RISC-V controller. 3D Object Detection based on LiDAR Point Clouds.☆16Mar 12, 2023Updated 2 years ago
- Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"☆11Apr 20, 2023Updated 2 years ago
- [DATE'2025, TCAD'2025] Terafly : A Multi-Node FPGA Based Accelerator Design for Efficient Cooperative Inference in LLMs☆28Nov 13, 2025Updated 3 months ago
- Hardware Description Language on FPGA☆10Sep 18, 2023Updated 2 years ago
- ☆13Dec 10, 2022Updated 3 years ago
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago
- Implementation of the OS-ROCKET algorithm for open set recognition for time series classifciation☆10Nov 21, 2021Updated 4 years ago
- ☆23May 6, 2025Updated 10 months ago
- Leetcode solutions☆14Updated this week
- ☆20Nov 23, 2022Updated 3 years ago
- ☆14Aug 9, 2023Updated 2 years ago
- ☆12Jun 4, 2024Updated last year
- A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.☆15Jan 14, 2022Updated 4 years ago
- 【IEEE IoTJ 2024】Heterogeneous Federated Learning: Client-side Collaborative Update Inter-Domain Generalization Method for Intelligent Fau…☆14Jun 23, 2025Updated 8 months ago
- Computer-aided VLSI System design, EEE 5022, National Taiwan University, 2018 Spring☆19Sep 19, 2018Updated 7 years ago
- Verilog implementation of a ultrasonic radar☆20Jan 7, 2018Updated 8 years ago
- RISC-V ISA based 32-bit processor written in HLS☆16Nov 7, 2019Updated 6 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆23May 7, 2024Updated last year
- Verdvana‘s Blog☆21Feb 3, 2026Updated last month
- Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.☆24Sep 21, 2021Updated 4 years ago