Alternatives and similar repositories for uvm:

Users that are interested in uvm are comparing it to the libraries listed below

• hjking / uvm_gen
  UVM Generator
  ☆44Updated 10 months ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆57Updated 4 years ago
• amiq-consulting / svaunit
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  ☆75Updated 4 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆58Updated 4 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆53Updated 8 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆53Updated 4 years ago
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆81Updated 3 years ago
• accellera-official / uvm-core
  ☆76Updated 6 months ago
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆52Updated 6 months ago
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆71Updated 3 years ago
• uvmdebug / uvm_debug
  UVM interactive debug library
  ☆32Updated 7 years ago
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆46Updated 10 years ago
• yuravg / uvm_tb_cross_bar
  SystemVerilog UVM testbench example
  ☆30Updated 10 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆109Updated last year
• raysalemi / Python4RTLVerification
  ☆150Updated 2 years ago
• dovstamler / uvm_agents
  UVM agents
  ☆78Updated 7 years ago
• kaushalmodi / custom_uvm_report_server
  Customized UVM Report Server
  ☆37Updated 5 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆119Updated last week
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆96Updated 3 years ago
• VerificationExcellence / SystemVerilogAssertions
  Examples and reference for System Verilog Assertions
  ☆83Updated 8 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 10 months ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆126Updated 6 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆67Updated 5 years ago
• chiggs / UVM
  Mirror of the Universal Verification Methodology from sourceforge
  ☆33Updated 10 years ago
• troyguo / dvcon_download
  Download proccedings from DVCon
  ☆22Updated 3 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆46Updated 2 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆50Updated 10 months ago
• chipsalliance / uvm-verilator
  ☆88Updated last year
• zhouchuanrui / JSONinSV
  JSON lib in Systemverilog
  ☆42Updated 3 years ago
• systemc / uvmc
  Connecting SystemC with SystemVerilog
  ☆38Updated 12 years ago