CHERI-enabled secure enclave that can be integrated as a subsytem on a system on chip.
☆43Oct 28, 2026Updated this week
Alternatives and similar repositories for mocha
Users that are interested in mocha are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Software, build flows and examples for the Sonata System☆15Sep 4, 2026Updated last month
- Design files and associated documentation for Sonata PCB, part of the Sunburst Project☆22Apr 1, 2025Updated last year
- An open silicon CHERIoT Ibex microcontroller chip☆19May 23, 2025Updated last year
- A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI☆54Sep 4, 2026Updated last month
- A RISC-V TestRIG Verification Engine based on QuickCheck☆12Oct 5, 2026Updated 3 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A DSL for formal verification of hardware and software systems using Rocq/Coq.☆12Updated this week
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆138Sep 14, 2026Updated last month
- Labs for the Ibex Demo System☆18Nov 18, 2023Updated 2 years ago
- OpenTitan FI formal verification framework☆19Aug 29, 2023Updated 3 years ago
- HiPU200 open-source version is a DNN accelerator, using RISC-V instruction set and customized vector/matrix extension.☆10Jan 7, 2022Updated 4 years ago
- 64-bit multicore Linux-capable RISC-V processor☆124Apr 28, 2025Updated last year
- Testing processors with Random Instruction Generation☆63Oct 5, 2026Updated 3 weeks ago
- UART verification using UVM with functional coverage, scoreboard, and test scenarios, simulated on QuestaSim.☆15Feb 26, 2025Updated last year
- virtual debug pod for RP2350 "Raspberry Pi Pico2" with no added hardware☆15Sep 12, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A Modified gem5 for Simulating Virtualized Systems☆11Mar 1, 2015Updated 11 years ago
- An RTL generator for a last-level shared inclusive TileLink cache controller☆27Aug 8, 2026Updated 2 months ago
- Search for JOP gadgets in your Risc-V applications with RaccoonV☆11Jun 22, 2023Updated 3 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆34Aug 28, 2023Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- A demo system for Ibex including debug support and some peripherals☆105Jul 16, 2026Updated 3 months ago
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆21Oct 10, 2026Updated 2 weeks ago
- ☆13Jul 5, 2026Updated 3 months ago
- A SystemVerilog source file pickler.☆62Oct 20, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A dependency management tool for hardware projects.☆401Oct 22, 2026Updated last week
- Pulp virtual platform☆24Jul 16, 2025Updated last year
- UVM verification platform for DW_apb_i2c IP core(Master Mode)☆15Aug 21, 2023Updated 3 years ago
- ☆12Nov 28, 2022Updated 3 years ago
- OpenTitan: Open source silicon root of trust☆3,718Updated this week
- FROST (FPGA RISC-V Open-sourced in SystemVerilog by TwoSigma)☆14Updated this week
- AIA IP compliant with the RISC-V AIA spec☆47Sep 7, 2026Updated last month
- Simulator for MIL-STD-1750A processors☆13Dec 5, 2016Updated 9 years ago
- ☆24Sep 26, 2025Updated last year
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…☆126Updated this week
- End-of-life (EOL) container analysis and scanning provided as a GitHub Action using https://github.com/xeol-io/xeol☆15Oct 23, 2024Updated 2 years ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆52Jul 11, 2025Updated last year
- PyCacheGen: A Highly Configurable Open-Source Generator for Synthesizable Caches☆18Dec 14, 2025Updated 10 months ago
- Fork of LLVM adding CHERI support☆78Updated this week
- Project ideas list for Google Summer of Code.☆18Jan 28, 2026Updated 9 months ago
- This is the main repository for the CHIPS Alliance OpenPRoT project☆19Updated this week