A RTL Synthesizer that can convert Verilog HDL into transistor-level netlist which can be simulated by Spice
☆12Jan 4, 2025Updated last year
Alternatives and similar repositories for ZSpice
Users that are interested in ZSpice are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- My notebook using mkdocs☆19Mar 12, 2025Updated last year
- 复旦数字集成电路设计自动化项目文档☆11Apr 12, 2025Updated last year
- ☆21Sep 29, 2025Updated 9 months ago
- A Swift Reimplementation of DanXi☆36Updated this week
- A dual-camera based on OminiVison 5460 for GoWin GW2A-55K Combat Board☆35Dec 6, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆45Apr 10, 2026Updated 2 months ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆71Aug 10, 2024Updated last year
- An open-source design automation framework for Field-coupled Nanotechnologies☆91Jun 30, 2026Updated last week
- Python implementation of an N-gram language model with Laplace smoothing and sentence generation.☆88Feb 9, 2018Updated 8 years ago
- Integrated_Circuits_and_Semiconductor 集成电路设计与半导体物理器件书籍☆177May 31, 2022Updated 4 years ago
- CPU Design Based on RISCV ISA☆138Jun 14, 2024Updated 2 years ago
- 一个开源的FPGA神经网络加速器。☆201Sep 4, 2023Updated 2 years ago
- EPFL logic synthesis benchmarks☆257May 6, 2026Updated 2 months ago
- C++ logic network library☆297Jun 30, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Fast inference from large lauguage models via speculative decoding☆918Aug 22, 2024Updated last year
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,183Jun 29, 2026Updated last week
- [ICML 2024] Break the Sequential Dependency of LLM Inference Using Lookahead Decoding☆1,339Mar 6, 2025Updated last year
- 32-bit Superscalar RISC-V CPU☆1,270Sep 18, 2021Updated 4 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆1,192Jun 30, 2026Updated last week
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,849Mar 24, 2021Updated 5 years ago
- Open-source implementation of AlphaEvolve☆6,633Mar 18, 2026Updated 3 months ago
- Yosys Open SYnthesis Suite☆4,566Updated this week
- 每个人都能看懂的大模型知识分享，LLMs春/秋招大模型面试前必看，让你和面试官侃侃而谈☆6,846May 31, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Pretrained Pytorch face detection (MTCNN) and facial recognition (InceptionResnet) models☆5,152Sep 16, 2025Updated 9 months ago
- A framework for few-shot evaluation of language models.☆13,205Jun 24, 2026Updated 2 weeks ago
- 解决Cursor在免费订阅期间出现以下提示的问题: Your request has been blocked as our system has detected suspicious activity / You've reached your trial reque…☆26,299May 14, 2026Updated last month
- 🧠「大模型」2小时完全从0训练64M的小参数LLM！Train a 64M-parameter LLM from scratch in just 2h!☆52,626Jun 28, 2026Updated last week
- 计算机自学指南☆73,521Feb 24, 2026Updated 4 months ago
- A list of Free Software network services and web applications which can be hosted on your own servers☆302,105Jun 30, 2026Updated last week