Alternatives and similar repositories for mips-cpu-and-microsystem

Users that are interested in mips-cpu-and-microsystem are comparing it to the libraries listed below

• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆86Updated 5 years ago
• rave1sking / single_cycle_RISCV_CPU_Design-32bit
  Verilog实现单周期非流水线32位RISCV指令集（45条）CPU
  ☆43Updated 4 years ago
• y0fy / CO-lab-material-CQU
  重庆大学计算机组成原理、硬件综合设计实验材料
  ☆38Updated 4 years ago
• cebarobot / UCAS-CALab-mycpu_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9
  ☆29Updated 4 years ago
• wlf1998 / CA
  计算机体系结构课程
  ☆19Updated 6 years ago
• kaitoukito / YSYX-NJU-Group
  YSYX RISC-V Project NJU Study Group
  ☆16Updated 10 months ago
• TheRainstorm / PiplineMIPS
  A 5-level pipelined MIPS CPU with branch prediction and great cache.
  ☆20Updated 4 years ago
• yuankong11 / MIPS_CPU
  一个支持AXI总线、支持Cache、包括所有非浮点MIPS 1指令、支持例外的静态五级流水MIPS CPU
  ☆11Updated 6 years ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• suisuisi / FPGAandGames
  FPGA实现各种小游戏，学习并快乐着
  ☆77Updated 3 years ago
• qing-2 / CPU
  单周期 8指令 MIPS32CPU
  ☆92Updated 3 years ago
• Bamboo1583 / sdram_controller
  使用verilog编写sdram控制器
  ☆12Updated 6 years ago
• spokeyjoe / LoongArchCPU
  A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.
  ☆28Updated last year
• wbbbbbb123 / Sram-controller-design-based-on-AHB-bus
  ☆20Updated 3 years ago
• luyufan498 / CPU_start_from_0
  从零开始设计一个CPU (Verilog)
  ☆59Updated 4 years ago
• cebarobot / UCAS-CALab-mycpu_axi_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab11~12 & 14~15
  ☆13Updated 4 years ago
• cquwei-cx / cpu20220108
  MIPS 57条指令五级流水线cpu (verilog实现+详细注释)
  ☆11Updated 3 years ago
• PrimeMHD / FPGA_ThreeLevelStorage
  【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。
  ☆118Updated 5 years ago
• RegiaYoung / RISC-V-CPU
  记录一下夏季学期计算机设计与实践课上写的RISC-V单周期CPU和RISC-V五级流水线CPU
  ☆14Updated 4 years ago
• redlightASl / Notes
  ☆85Updated 3 months ago
• TheRainstorm / CO_ext_lab-CQU
  重庆大学计组（硬综）拓展实验；
  ☆21Updated 4 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆53Updated 3 years ago
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆153Updated 6 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆32Updated 3 years ago
• Tan-YiFan / DigitalLogic-Autumn2020
  复旦大学 数字逻辑与部件设计实验 2020秋
  ☆53Updated 3 years ago
• TranquilRock / RISC-V-PipelineCPU
  NTU Computer Architecture 2021 - CPU with Single issue, L1-cache
  ☆11Updated 3 years ago
• alireza-shirzad / Cordic_tanh
  Verilog and matlab implementation of tanh using Cordic algorithm
  ☆11Updated 5 years ago
• Boucii / RISC-V-Ladder
  An out-of-order, dual issueed RISC-V core and SOC, a working project.
  ☆11Updated 2 years ago
• chsgcxy / messy_notes
  all kind of notes, I maybe sort this in the future
  ☆13Updated 2 months ago
• RPTU-EIS / RISCV-Core
  5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
  ☆13Updated last year