luyufan498/CPU_start_from_0 external links

---

GitHub - View repository

GitHub.dev - Open in online code editor

Star history - Growth chart over time

deps.dev - Dependencies and security vulnerabilities

Gitingest - Export source code for LLM usage

Repomix - Export source code for LLM usage

uithub - Export source code for LLM usage

Close

luyufan498/CPU_start_from_0

Readme badge preview -

If you own this repo, copy the snippet below and add it to your README.md

---

Copy

[![RelatedRepos](https://img.shields.io/badge/related-repos-yellow)](https://relatedrepos.com/gh/luyufan498/CPU_start_from_0)

Close

luyufan498 / CPU_start_from_0View on GitHubMore

• External links
• Readme badge

从零开始设计一个CPU (Verilog)

☆62Mar 14, 2021Updated 5 years ago

Alternatives and similar repositories for CPU_start_from_0

Users that are interested in CPU_start_from_0 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.

• lvyufeng / step_into_mips

  View on GitHub
  一步一步写MIPS CPU
  ☆882Jun 5, 2026Updated 3 months ago
• 6rus / sms2mail

  View on GitHub
  Android App : transfer sms received to your mail adress
  ☆11Nov 25, 2019Updated 6 years ago
• Raamakrishnan / verilog-filelist-parser

  View on GitHub
  A Verilog Filelist parser in Rust
  ☆11Mar 25, 2022Updated 4 years ago
• markos-stefanidis / FPGA-Based-HDR-algorithm

  View on GitHub
  Hardware implementation of HDR image producing algorithm
  ☆16Sep 30, 2022Updated 3 years ago
• OpenBanboo / High-Performance-ALU

  View on GitHub
  RTL Design and Implementation of High Performance Algorithm Logic Units
  ☆15Oct 1, 2019Updated 6 years ago
• Managed Database hosting by DigitalOcean • Ad
  PostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
• qinghew / SDGAN

  View on GitHub
  基于自判别循环生成对抗网络的人脸图像翻译
  ☆12Feb 14, 2022Updated 4 years ago
• TranquilRock / RISC-V-PipelineCPU

  View on GitHub
  NTU Computer Architecture 2021 - CPU with Single issue, L1-cache
  ☆11Jan 24, 2022Updated 4 years ago
• Timothy-Liuxf / PipelineCPU

  View on GitHub
  清华大学电子工程系数字逻辑与处理器基础实验大作业——流水线 CPU
  ☆13Aug 8, 2021Updated 5 years ago
• alvations / DLTK

  View on GitHub
  Deutsch Language Tool Kit
  ☆12Aug 31, 2015Updated 11 years ago
• yiwangchunyu / AI-RISC

  View on GitHub
  Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects
  ☆15Jun 28, 2021Updated 5 years ago
• IntelliKernel / Dynaseal

  View on GitHub
  Dynaseal is a dynamic API key management system designed to secure communications and identity verification for large model services. It …
  ☆12Oct 30, 2024Updated last year
• Qingzheng-Wang / PipelineCPU

  View on GitHub
  2022WHU计算机系统综合设计 基于RISCV的五级流水线CPU Five stage CPU implement based on RISC-V
  ☆13Oct 31, 2023Updated 2 years ago
• SinnLiu / CPU_Design_MIPS

  View on GitHub
  《CPU设计实战》学习记录及代码
  ☆15Dec 30, 2023Updated 2 years ago
• zhangly / azpr_cpu

  View on GitHub
  用Altera FPGA芯片自制CPU
  ☆42Aug 10, 2014Updated 12 years ago
• Deploy to Railway using AI coding agents - Free Credits Offer • Ad
  Use Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
• whc2uestc / BD3_FPGA

  View on GitHub
  新一代北斗卫星导航监测接收机的FPGA实现
  ☆31May 17, 2016Updated 10 years ago
• whik / UART_Demo_Verilog

  View on GitHub
  基于Verilog实现的串口发送程序，带奇偶校验位。
  ☆12Aug 23, 2019Updated 7 years ago
• unicornx / riscv-operating-system-mooc

  View on GitHub
  ☆73May 10, 2026Updated 4 months ago
• WilliamWuLH / VHDL_CPU

  View on GitHub
  湖南大学数字电路与逻辑设计大实验使用VHDL完成简易CPU设计
  ☆20Dec 7, 2020Updated 5 years ago
• study34668 / MiniMIPS32

  View on GitHub
  MiniMIPS32 五级流水线处理器 Verilog建模和Logisim建模
  ☆12Dec 28, 2020Updated 5 years ago
• LordDeng / adas-auto-braking

  View on GitHub
  Advanced Driver Assistance Systems: Assignment Part II (Auto Emergency Braking System in Matlab Simulink)
  ☆10Jan 3, 2019Updated 7 years ago
• jacobcx / MetaWares

  View on GitHub
  MPC5746R AUTOSAR demo without SWC
  ☆16Sep 13, 2018Updated 8 years ago
• LC044 / CPU

  View on GitHub
  五级流水线CPU设计
  ☆15Jun 2, 2023Updated 3 years ago
• Yongxiang-Guo / Verilog_spi_flash

  View on GitHub
  SPI通信实现FLASH读写
  ☆17Mar 18, 2020Updated 6 years ago
• Deploy open-source AI quickly and easily - Special Bonus Offer • Ad
  Runpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
• jhdjames37 / RISC-V-CPU-simple

  View on GitHub
  清华大学《计算机组成原理》大实验——五级流水线 RISC-V 处理器。「奋战三星期，造台计算机」
  ☆23Mar 11, 2023Updated 3 years ago
• fallen / tinycpu

  View on GitHub
  Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes.
  ☆36Jan 17, 2012Updated 14 years ago
• sunxin18 / nvim

  View on GitHub
  ☆10Apr 20, 2026Updated 5 months ago
• cnyangkun / nscscc2018

  View on GitHub
  nscscc2018
  ☆27Oct 11, 2018Updated 7 years ago
• muzilinxi90 / OpenMIPS

  View on GitHub
  OpenMIPS——《自己动手写CPU》处理器部分
  ☆22Mar 4, 2017Updated 9 years ago
• kyak / stellaris_ert

  View on GitHub
  Simulink (Embedded Coder) Target for TI Stellaris LaunchPad
  ☆18Mar 20, 2019Updated 7 years ago
• OpenAADL / polyorb-hi-c

  View on GitHub
  PolyORB-HI/C runtime for Ocarina, supports POSIX, RTEMS, Xenomai, XtratuM RTOS
  ☆12Sep 22, 2022Updated 4 years ago
• AU20GradProject / OS

  View on GitHub
  Autosar OSEK/VDX Operating system
  ☆16May 13, 2020Updated 6 years ago
• Singein / Pycman

  View on GitHub
  Python package manager
  ☆10Jul 11, 2021Updated 5 years ago
• Managed Kubernetes at scale on DigitalOcean • Ad
  DigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
• cishudian / mpc5744P_CAN_BootLoader

  View on GitHub
  mpc5744P_CAN_BootLoader
  ☆20Jun 1, 2019Updated 7 years ago
• HypoX64 / EE-Codes-of-SCNU

  View on GitHub
  Electronic Engineering/Communication Engineering Course Design of SCNU(华南师范大学电子信息类/通信工程专业，课程设计/综合实验设计代码及相关文件)
  ☆32Aug 29, 2020Updated 6 years ago
• Lyncien / RISC-V-32I

  View on GitHub
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆91Nov 28, 2019Updated 6 years ago
• PaulZhe / SchoolMap

  View on GitHub
  校园导航系统，数据结构课设
  ☆20Jun 26, 2019Updated 7 years ago
• liuqdev / 8-bits-RISC-CPU-Verilog

  View on GitHub
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆169Jan 20, 2019Updated 7 years ago
• fangyzh26 / FIFO

  View on GitHub
  包括同步FIFO（输入输出位宽相同），异步FIFO（输入输出位宽相同），异步FIFO（能实现输出数据位宽是输入数据位宽的1/2或2倍）
  ☆25Nov 7, 2022Updated 3 years ago
• Cheb57 / binutils-tricore

  View on GitHub
  GNU/binutils revision 2.13 targetting Infineon tricore CPU architecture
  ☆22Jan 30, 2019Updated 7 years ago