Alternatives and similar repositories for CPU_start_from_0

Users that are interested in CPU_start_from_0 are comparing it to the libraries listed below

• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆160Updated 6 years ago
• xupsh / Digital-Design-Lab
  ☆228Updated 4 years ago
• lvyufeng / step_into_mips
  一步一步写MIPS CPU
  ☆847Updated 4 years ago
• renyangang / riscv-mcu
  This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral…
  ☆77Updated 8 months ago
• qing-2 / CPU
  单周期 8指令 MIPS32CPU
  ☆96Updated last week
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆297Updated 4 months ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆113Updated 3 years ago
• Edragon / FPGA_DOCS
  ☆143Updated 6 years ago
• redlightASl / Notes
  ☆86Updated 3 weeks ago
• Starrynightzyq / Nexys4DDR-ARM-M3-Plate-Recognition
  车牌识别,FPGA,2019全国大学生集成电路创新创业大赛
  ☆146Updated 6 years ago
• WeitaoZhu / Integrated_Circuits_and_Semiconductor
  Integrated_Circuits_and_Semiconductor 集成电路设计与半导体物理器件书籍
  ☆134Updated 3 years ago
• zach0zhang / Single_instruction_cycle_OpenMIPS
  通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
  ☆207Updated 3 years ago
• whik / e200_opensource
  The Ultra-Low Power RISC Core
  ☆49Updated 6 years ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆86Updated 6 years ago
• Nitcloud / Digital-IDE
  在vscode上的数字设计开发插件
  ☆392Updated 2 years ago
• jerrylioon / Solutions-to-HDLbits-Verilog-sets
  Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).
  ☆94Updated 2 years ago
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆72Updated 2 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆136Updated 2 years ago
• Xinyang-ZHANG / RISC_V_RV32I_5stage_pipeline
  5 stage pipeline, single cycle risc-V implementation
  ☆27Updated last year
• Azalea8 / riscv_cpu
  riscv指令集，单周期以及五级流水线CPU
  ☆102Updated last year
• suisuisi / FPGAandGames
  FPGA实现各种小游戏，学习并快乐着
  ☆78Updated 3 years ago
• OSCPU / NutShell-doc
  ☆125Updated 3 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆33Updated 3 years ago
• Z-Y00 / Examples-in-book-write-your-own-cpu
  《自己动手写CPU》一书附带的文件
  ☆87Updated 7 years ago
• rave1sking / single_cycle_RISCV_CPU_Design-32bit
  Verilog实现单周期非流水线32位RISCV指令集（45条）CPU
  ☆42Updated 5 years ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆153Updated last month
• BigPig-Bro / udp_gmii_ov5640
  本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛（高云赛道）项目，题目基于高云FPGA的多路网络视频监控编码系统。
  ☆62Updated 2 years ago
• OSCPU / ysyx-workbench
  ☆159Updated 3 weeks ago
• xiaop1 / Verilog-Practice
  HDLBits website practices & solutions
  ☆772Updated 2 years ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆66Updated 3 years ago