luyufan498 / CPU_start_from_0
从零开始设计一个CPU (Verilog)
☆52Updated 3 years ago
Alternatives and similar repositories for CPU_start_from_0:
Users that are interested in CPU_start_from_0 are comparing it to the libraries listed below
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。☆141Updated 6 years ago
- ☆214Updated 3 years ago
- 车牌识别,FPGA,2019全国大学生集成电路创新创业大赛☆134Updated 5 years ago
- riscv指令集,单周期以及五级流水线CPU☆43Updated 2 months ago
- 一步一步写MIPS CPU☆783Updated 3 years ago
- 《自己动手写CPU》一书附带的文件☆79Updated 7 years ago
- ☆69Updated 2 weeks ago
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆72Updated 5 years ago
- 单周期 8指令 MIPS32CPU☆89Updated 2 years ago
- Integrated_Circuits_and_Semiconductor 集成电路设计与半导体物理器件书籍☆82Updated 2 years ago
- CPU Design Based on RISCV ISA☆92Updated 8 months ago
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆60Updated 2 years ago
- 这是我所开发的两个项目,包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统☆85Updated 7 years ago
- ☆139Updated 2 weeks ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆103Updated 2 years ago
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛(高云赛道)项目,题目基于高云FPGA的多路网络视频监控编码系统。☆46Updated last year
- This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral…☆46Updated 3 months ago
- 数字IC设计 学习笔记☆129Updated 3 years ago
- AXI协议规范中 文翻译版☆140Updated 2 years ago
- The Ultra-Low Power RISC Core☆47Updated 5 years ago
- NSCSCC 信息整合☆232Updated 4 years ago
- 记录一下夏季学期计算机设计与实践课上写的RISC-V单周期CPU和RISC-V五级流水线CPU☆12Updated 3 years ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆26Updated 2 years ago
- ☆16Updated 2 years ago
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆121Updated 4 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆62Updated 2 years ago
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆22Updated last year
- 通过学习《自己动手写CPU》,将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS(五级流水线结构),简化成单指令周期实现的处理器☆195Updated 3 years ago
- 用verilog设计8位cpu☆7Updated 4 years ago
- 《FPGA应用开发和仿真》(机械工业出版社2018年第1版 ISBN:9787111582786)的源码。Source Code of the book FPGA Application Development and Simulation(CHS).☆130Updated 4 months ago