Alternatives and similar repositories for CA

Users that are interested in CA are comparing it to the libraries listed below

• cebarobot / UCAS-CALab-mycpu_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9
  ☆34Updated 4 years ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆86Updated 6 years ago
• wzp21142 / mips-cpu-and-microsystem
  基于Verilog实现的三个MIPS架构CPU项目,按顺序实现了单周期,多周期以及基于多周期的微系统. Three Verilog-based MIPS CPU projects, simulate pipelined cpu based on mips instructi…
  ☆17Updated 4 years ago
• chsgcxy / messy_notes
  all kind of notes, I maybe sort this in the future
  ☆13Updated 5 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• CherrySprings / CherrySprings
  ☆19Updated 2 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆136Updated 2 years ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆42Updated 7 years ago
• lijyhh / LEGv8
  A simple implementation about LEGv8 instruction set using Verilog HDL.
  ☆11Updated 3 years ago
• zhhangBian / BOOM_chip
  乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四
  ☆18Updated last year
• luzhixing12345 / archlab
  NUDT 高级体系结构实验
  ☆35Updated last year
• nicolaswilde / UCAS-Advanced-Computer-Architecture-OpenROAD-flow
  中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程
  ☆30Updated 5 years ago
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆182Updated 4 years ago
• sailordiary / computer-systems-ucas
  中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
  ☆32Updated 8 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆146Updated last year
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆33Updated 3 years ago
• TYOD-SOC / RISCV-Accelerator
  ☆37Updated 7 years ago
• VenciFreeman / RISC-V
  A simple RISC-V CPU written in Verilog.
  ☆69Updated last year
• hypocrasy / NPUSoC
  第四届全国大学生嵌入式比赛SoC
  ☆11Updated 3 years ago
• kaitoukito / YSYX-NJU-Group
  YSYX RISC-V Project NJU Study Group
  ☆16Updated last year
• jensen-yan / kisscpu
  国科大一生一芯第二期: RISCV-64 五级流水线CPU
  ☆18Updated 4 years ago
• OSCPU / ysyxSoC
  ☆92Updated 4 months ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆66Updated 3 years ago
• OSCPU / ysyx-workbench
  ☆160Updated last month
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆25Updated last year
• Boucii / RISC-V-Ladder
  An out-of-order, dual issueed RISC-V core and SOC, a working project.
  ☆10Updated 2 years ago
• lmxyy / Computer-Architecture-Task-2
  Riscv32 CPU Project
  ☆95Updated 8 years ago
• zach0zhang / Single_instruction_cycle_OpenMIPS
  通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
  ☆207Updated 3 years ago
• RPTU-EIS / RISCV-Core
  5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
  ☆13Updated last month
• loongson-education / nscscc-wiki
  NSCSCC 信息整合
  ☆252Updated 4 years ago