Alternatives and similar repositories for CA:

Users that are interested in CA are comparing it to the libraries listed below

• CherrySprings / CherrySprings
  ☆17Updated last year
• chsgcxy / messy_notes
  all kind of notes, I maybe sort this in the future
  ☆10Updated last month
• jensen-yan / kisscpu
  国科大一生一芯第二期: RISCV-64 五级流水线CPU
  ☆17Updated 3 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆49Updated 2 years ago
• cebarobot / UCAS-CALab-mycpu_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9
  ☆26Updated 3 years ago
• nicolaswilde / UCAS-Advanced-Computer-Architecture-OpenROAD-flow
  中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程
  ☆24Updated 4 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 4 years ago
• kaitoukito / YSYX-NJU-Group
  YSYX RISC-V Project NJU Study Group
  ☆15Updated 2 months ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆39Updated 7 years ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆72Updated 5 years ago
• sailordiary / computer-systems-ucas
  中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
  ☆32Updated 7 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆34Updated 5 years ago
• redlightASl / Notes
  ☆71Updated last month
• OSCPU / yosys-sta
  ☆62Updated 3 months ago
• OSCPU / NutShell-doc
  ☆122Updated 2 years ago
• BATManVSGig / hello-world
  ☆21Updated 6 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆47Updated last year
• lijyhh / LEGv8
  A simple implementation about LEGv8 instruction set using Verilog HDL.
  ☆11Updated 2 years ago
• meton-robean / ResearchNote
  通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …
  ☆75Updated 4 years ago
• cebarobot / UCAS-CALab-mycpu_axi_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab11~12 & 14~15
  ☆12Updated 4 years ago
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆106Updated 5 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆26Updated 2 years ago
• OSCPU / ysyxSoC
  ☆80Updated last month
• yuhanzhu612 / OSCPU
  我的一生一芯项目
  ☆16Updated 3 years ago
• Z-Y00 / Examples-in-book-write-your-own-cpu
  《自己动手写CPU》一书附带的文件
  ☆80Updated 7 years ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆52Updated 7 months ago
• spokeyjoe / LoongArchCPU
  A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.
  ☆22Updated 10 months ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆63Updated 2 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆38Updated last year
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆26Updated 5 years ago