freecores / mcs-4Links
4004 CPU and MCS-4 family chips
☆44Updated 11 years ago
Alternatives and similar repositories for mcs-4
Users that are interested in mcs-4 are comparing it to the libraries listed below
Sorting:
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- IceChips is a library of all common discrete logic devices in Verilog☆146Updated 2 weeks ago
- Basic USB 1.1 Host Controller for small FPGAs☆95Updated 5 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆65Updated 4 months ago
- Example Verilog code for Ulx3s☆42Updated 3 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆61Updated 2 years ago
- Update IceStudio to support ColorLight 5A-75X, i5 and ICeSugar Pro FPGA boards☆49Updated 2 years ago
- 65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface☆73Updated 2 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆192Updated 6 years ago
- iCESugar series FPGA dev board☆185Updated last month
- Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).☆54Updated 2 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆66Updated this week
- Featherweight RISC-V implementation☆53Updated 3 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆52Updated last year
- A compact USB HID host FPGA core supporting keyboards, mice and gamepads.☆139Updated 6 months ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆32Updated 2 years ago
- Documenting the Lattice ECP5 bit-stream format.☆55Updated 2 years ago
- Tools for FPGA development.☆48Updated 2 months ago
- A Video display simulator☆173Updated 5 months ago
- Another tiny RISC-V implementation☆59Updated 4 years ago
- HDMI core in Chisel HDL☆51Updated last year
- ☆13Updated 3 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆107Updated last month
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆99Updated last week
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Linux capable RISC-V SoC designed to be readable and useful.☆152Updated 4 months ago
- SoftCPU/SoC engine-V☆55Updated 7 months ago
- Easy-to-use JTAG TAP and Debug Controller core written in Verilog☆33Updated 6 years ago
- Portable HyperRAM controller☆60Updated 10 months ago