Tutorial for analog input digitalization by the Xilinx Zynq XADC utilizing the DMA and data streaming to a PC over the network.
☆37Apr 4, 2026Updated last month
Alternatives and similar repositories for Zynq-XADC-DMA-lwIP
Users that are interested in Zynq-XADC-DMA-lwIP are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application☆82Mar 21, 2026Updated last month
- Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.☆29Mar 24, 2021Updated 5 years ago
- Experimental Xilinx Artix-7 driven Data Center Security Communication Module☆67Dec 11, 2025Updated 5 months ago
- Use of the PID library to send commands to dc servo and view results using pyplot☆16Mar 5, 2017Updated 9 years ago
- Repository for the Introduction to FPGA Programming Using Xilinx Vivado and VHDL PhD course at University of Torino, Physics Department.☆20Jul 4, 2025Updated 10 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 关于CIC滤波器、ISOP补偿器、HB滤波器的相关Matlab仿真与FPGA工程☆15Dec 25, 2023Updated 2 years ago
- ISP☆13Nov 25, 2023Updated 2 years ago
- 文档编写☆13Sep 19, 2020Updated 5 years ago
- ☆12Dec 10, 2025Updated 5 months ago
- Originally a port of Scintilla to OpenGL, now kindof a livecoding tool.☆14Feb 7, 2015Updated 11 years ago
- Hardware Description Language Translator☆19May 3, 2026Updated 2 weeks ago
- Example project of a C++ native code Python3 module with Pybind11 managed by CMake and vcpkg☆12Jan 9, 2019Updated 7 years ago
- Setup guides for Raptor Talos II Secure Workstation based on IBM's Power9 CPU.☆15Sep 7, 2025Updated 8 months ago
- CMSIS-DAP debug probe based on STM32F042☆10May 19, 2019Updated 7 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Hardware Implementation of low-bit rate Codec, Codec2 in Verilog RTL on Cyclone IV FPGA.☆15Mar 29, 2020Updated 6 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆31Jan 17, 2026Updated 4 months ago
- Saltanat bot Бесплатный облачный сервис☆10Nov 4, 2020Updated 5 years ago
- Let's write an OS which can run on ARM in Rust from scratch! (🚧WIP)☆18Mar 13, 2022Updated 4 years ago
- grblHAL plugin for networking protocols (Telnet, WebSocket, FTP, HTTP) and related utilities on top of LwIP☆14May 6, 2026Updated 2 weeks ago
- Some commonly used embedded system libraries.☆10Nov 3, 2020Updated 5 years ago
- ☆14Dec 18, 2022Updated 3 years ago
- FPGA纯逻辑实现modbus通信☆24Sep 5, 2022Updated 3 years ago
- A fast C++ Madelbrot renderer using AVX2 extensions☆13Oct 7, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- tuya_iot_sdk_for_RTL8710BN☆11Mar 8, 2020Updated 6 years ago
- GDB Stub for RT-Thread(already in RT-Thread master)☆17Jan 10, 2015Updated 11 years ago
- 🇯 JSON encoder and decoder in pure SystemVerilog☆15Jul 7, 2024Updated last year
- A design for TinyTapeout☆19Sep 23, 2022Updated 3 years ago
- Portable PLC PID autotuner using the relay method written in iec61131-3 structured text format☆16Jan 30, 2019Updated 7 years ago
- SpaceWire☆14Jul 17, 2014Updated 11 years ago
- My self-designed ZYNQ-7010 4-layer developement board.☆35Jul 25, 2021Updated 4 years ago
- RT-Thread network samples☆13Apr 4, 2023Updated 3 years ago
- The code for an FPGA softcore comparison☆11Jun 21, 2020Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Learn how to create your own 32-bit system from scratch.☆14Feb 15, 2022Updated 4 years ago
- W25Qxx Family Driver☆12Sep 28, 2024Updated last year
- 基于verilog实现了ISP图像处理IP(Altera EP4CE6)☆24Jul 15, 2022Updated 3 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆22Nov 9, 2025Updated 6 months ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆19Nov 16, 2023Updated 2 years ago
- network packets capture in C language based on libpcap☆15Sep 23, 2022Updated 3 years ago
- Trading Dollar cost averaging☆10Mar 6, 2023Updated 3 years ago